Merge branch 'master' of master.kernel.org:/pub/scm/linux/kernel/git/davem/net-2.6 (5403c8a2) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/net/bnx2x/bnx2x.h

+2 −2

Original line number	Diff line number	Diff line
		@@ -22,8 +22,8 @@
		* (you will need to reboot afterwards) */
		/* #define BNX2X_STOP_ON_ERROR */

		#define DRV_MODULE_VERSION "1.62.00-4"
		#define DRV_MODULE_RELDATE "2011/01/18"
		#define DRV_MODULE_VERSION "1.62.00-5"
		#define DRV_MODULE_RELDATE "2011/01/30"
		#define BNX2X_BC_VER 0x040200

		#define BNX2X_MULTI_QUEUE

drivers/net/bnx2x/bnx2x_link.c

+18 −47

Original line number	Diff line number	Diff line
		@@ -3948,48 +3948,6 @@ static u8 bnx2x_8073_8727_external_rom_boot(struct bnx2x *bp,
		return rc;
		}

		static void bnx2x_8073_set_xaui_low_power_mode(struct bnx2x *bp,
		struct bnx2x_phy *phy)
		{
		u16 val;
		bnx2x_cl45_read(bp, phy,
		MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, &val);

		if (val == 0) {
		/* Mustn't set low power mode in 8073 A0 */
		return;
		}

		/* Disable PLL sequencer (use read-modify-write to clear bit 13) */
		bnx2x_cl45_read(bp, phy,
		MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
		val &= ~(1<<13);
		bnx2x_cl45_write(bp, phy,
		MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);

		/* PLL controls */
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805E, 0x1077);
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805D, 0x0000);
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805C, 0x030B);
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805B, 0x1240);
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x805A, 0x2490);

		/* Tx Controls */
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A7, 0x0C74);
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A6, 0x9041);
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80A5, 0x4640);

		/* Rx Controls */
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FE, 0x01C4);
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FD, 0x9249);
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, 0x80FC, 0x2015);

		/* Enable PLL sequencer (use read-modify-write to set bit 13) */
		bnx2x_cl45_read(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, &val);
		val \|= (1<<13);
		bnx2x_cl45_write(bp, phy, MDIO_XS_DEVAD, MDIO_XS_PLL_SEQUENCER, val);
		}

		/******************************************************************/
		/* BCM8073 PHY SECTION */
		/******************************************************************/
		@@ -4148,8 +4106,6 @@ static u8 bnx2x_8073_config_init(struct bnx2x_phy *phy,

		bnx2x_8073_set_pause_cl37(params, phy, vars);

		bnx2x_8073_set_xaui_low_power_mode(bp, phy);

		bnx2x_cl45_read(bp, phy,
		MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);

		@@ -6519,6 +6475,18 @@ static void bnx2x_848xx_set_link_led(struct bnx2x_phy *phy,
		MDIO_PMA_DEVAD,
		MDIO_PMA_REG_8481_LED1_MASK,
		0x80);

		/* Tell LED3 to blink on source */
		bnx2x_cl45_read(bp, phy,
		MDIO_PMA_DEVAD,
		MDIO_PMA_REG_8481_LINK_SIGNAL,
		&val);
		val &= ~(7<<6);
		val \|= (1<<6); /* A83B[8:6]= 1 */
		bnx2x_cl45_write(bp, phy,
		MDIO_PMA_DEVAD,
		MDIO_PMA_REG_8481_LINK_SIGNAL,
		val);
		}
		break;
		}
		@@ -7720,10 +7688,13 @@ static u8 bnx2x_8073_common_init_phy(struct bnx2x *bp,
		struct bnx2x_phy phy[PORT_MAX];
		struct bnx2x_phy *phy_blk[PORT_MAX];
		u16 val;
		s8 port;
		s8 port = 0;
		s8 port_of_path = 0;

		bnx2x_ext_phy_hw_reset(bp, 0);
		u32 swap_val, swap_override;
		swap_val = REG_RD(bp, NIG_REG_PORT_SWAP);
		swap_override = REG_RD(bp, NIG_REG_STRAP_OVERRIDE);
		port ^= (swap_val && swap_override);
		bnx2x_ext_phy_hw_reset(bp, port);
		/* PART1 - Reset both phys */
		for (port = PORT_MAX - 1; port >= PORT_0; port--) {
		u32 shmem_base, shmem2_base;

drivers/net/bnx2x/bnx2x_main.c

+11 −7

Original line number	Diff line number	Diff line
		@@ -5296,10 +5296,6 @@ static int bnx2x_init_hw_common(struct bnx2x *bp, u32 load_code)
		}
		}

		bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
		bp->common.shmem_base,
		bp->common.shmem2_base);

		bnx2x_setup_fan_failure_detection(bp);

		/* clear PXP2 attentions */
		@@ -5503,9 +5499,6 @@ static int bnx2x_init_hw_port(struct bnx2x *bp)

		bnx2x_init_block(bp, MCP_BLOCK, init_stage);
		bnx2x_init_block(bp, DMAE_BLOCK, init_stage);
		bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
		bp->common.shmem_base,
		bp->common.shmem2_base);
		if (bnx2x_fan_failure_det_req(bp, bp->common.shmem_base,
		bp->common.shmem2_base, port)) {
		u32 reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 :
		@@ -8379,6 +8372,17 @@ static void __devinit bnx2x_get_port_hwinfo(struct bnx2x *bp)
		(ext_phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
		bp->mdio.prtad =
		XGXS_EXT_PHY_ADDR(ext_phy_config);

		/*
		* Check if hw lock is required to access MDC/MDIO bus to the PHY(s)
		* In MF mode, it is set to cover self test cases
		*/
		if (IS_MF(bp))
		bp->port.need_hw_lock = 1;
		else
		bp->port.need_hw_lock = bnx2x_hw_lock_required(bp,
		bp->common.shmem_base,
		bp->common.shmem2_base);
		}

		static void __devinit bnx2x_get_mac_hwinfo(struct bnx2x *bp)

drivers/net/can/Kconfig

+1 −1

Original line number	Diff line number	Diff line
		@@ -23,7 +23,7 @@ config CAN_SLCAN

		As only the sending and receiving of CAN frames is implemented, this
		driver should work with the (serial/USB) CAN hardware from:
		www.canusb.com / www.can232.com / www.mictronic.com / www.canhack.de
		www.canusb.com / www.can232.com / www.mictronics.de / www.canhack.de

		Userspace tools to attach the SLCAN line discipline (slcan_attach,
		slcand) can be found in the can-utils at the SocketCAN SVN, see

include/linux/Kbuild

+1 −0

Original line number	Diff line number	Diff line
		header-y += byteorder/
		header-y += can/
		header-y += caif/
		header-y += dvb/
		header-y += hdlc/
		header-y += isdn/