tools headers uapi: Synchronize i915_drm.h

 */

#define I915_PARAM_CS_TIMESTAMP_FREQUENCY 51

/*

 * Once upon a time we supposed that writes through the GGTT would be

 * immediately in physical memory (once flushed out of the CPU path). However,

 * on a few different processors and chipsets, this is not necessarily the case

 * as the writes appear to be buffered internally. Thus a read of the backing

 * storage (physical memory) via a different path (with different physical tags

 * to the indirect write via the GGTT) will see stale values from before

 * the GGTT write. Inside the kernel, we can for the most part keep track of

 * the different read/write domains in use (e.g. set-domain), but the assumption

 * of coherency is baked into the ABI, hence reporting its true state in this

 * parameter.

 *

 * Reports true when writes via mmap_gtt are immediately visible following an

 * lfence to flush the WCB.

 *

 * Reports false when writes via mmap_gtt are indeterminately delayed in an in

 * internal buffer and are _not_ immediately visible to third parties accessing

 * directly via mmap_cpu/mmap_wc. Use of mmap_gtt as part of an IPC

 * communications channel when reporting false is strongly disadvised.

 */

#define I915_PARAM_MMAP_GTT_COHERENT	52

typedef struct drm_i915_getparam {

	__s32 param;

	/*