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Unverified Commit 531a1b62 authored by Boris Brezillon's avatar Boris Brezillon Committed by Maxime Ripard
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drm/vc4: Report HVS underrun errors 



Add a debugfs entry and helper for reporting HVS underrun errors as
well as helpers for masking and unmasking the underrun interrupts.
Add an IRQ handler and initial IRQ configuration.
Rework related register definitions to take the channel number.

Signed-off-by: default avatarBoris Brezillon <boris.brezillon@bootlin.com>
Signed-off-by: default avatarPaul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: default avatarEric Anholt <eric@anholt.net>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190220155124.25022-2-paul.kocialkowski@bootlin.com
parent dbfbe717

drivers/gpu/drm/vc4/vc4_crtc.c

+8 −0
Original line number Diff line number Diff line
@@ -834,6 +834,14 @@ static void vc4_crtc_handle_page_flip(struct vc4_crtc *vc4_crtc) 
		drm_crtc_send_vblank_event(crtc, vc4_crtc->event);

		vc4_crtc->event = NULL;

		drm_crtc_vblank_put(crtc);



		/* Wait for the page flip to unmask the underrun to ensure that

		 * the display list was updated by the hardware. Before that

		 * happens, the HVS will be using the previous display list with

		 * the CRTC and encoder already reconfigured, leading to

		 * underruns. This can be seen when reconfiguring the CRTC.

		 */

		vc4_hvs_unmask_underrun(dev, vc4_crtc->channel);

	}

	spin_unlock_irqrestore(&dev->event_lock, flags);

}

drivers/gpu/drm/vc4/vc4_debugfs.c

+1 −0
Original line number Diff line number Diff line
@@ -23,6 +23,7 @@ static const struct drm_info_list vc4_debugfs_list[] = { 
	{"vec_regs", vc4_vec_debugfs_regs, 0},

	{"txp_regs", vc4_txp_debugfs_regs, 0},

	{"hvs_regs", vc4_hvs_debugfs_regs, 0},

	{"hvs_underrun",  vc4_hvs_debugfs_underrun, 0},

	{"crtc0_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)0},

	{"crtc1_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)1},

	{"crtc2_regs", vc4_crtc_debugfs_regs, 0, (void *)(uintptr_t)2},

drivers/gpu/drm/vc4/vc4_drv.h

+10 −0
Original line number Diff line number Diff line
@@ -184,6 +184,13 @@ struct vc4_dev { 
	/* Bitmask of the current bin_alloc used for overflow memory. */

	uint32_t bin_alloc_overflow;



	/* Incremented when an underrun error happened after an atomic commit.

	 * This is particularly useful to detect when a specific modeset is too

	 * demanding in term of memory or HVS bandwidth which is hard to guess

	 * at atomic check time.

	 */

	atomic_t underrun;



	struct work_struct overflow_mem_work;



	int power_refcount;
@@ -767,6 +774,9 @@ void vc4_irq_reset(struct drm_device *dev); 
extern struct platform_driver vc4_hvs_driver;

void vc4_hvs_dump_state(struct drm_device *dev);

int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused);

int vc4_hvs_debugfs_underrun(struct seq_file *m, void *unused);

void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel);

void vc4_hvs_mask_underrun(struct drm_device *dev, int channel);



/* vc4_kms.c */

int vc4_kms_load(struct drm_device *dev);

drivers/gpu/drm/vc4/vc4_hvs.c

+95 −0
Original line number Diff line number Diff line
@@ -22,6 +22,7 @@ 
 * each CRTC.

 */



#include <drm/drm_atomic_helper.h>

#include <linux/component.h>

#include "vc4_drv.h"

#include "vc4_regs.h"
@@ -102,6 +103,18 @@ int vc4_hvs_debugfs_regs(struct seq_file *m, void *unused) 


	return 0;

}



int vc4_hvs_debugfs_underrun(struct seq_file *m, void *data)

{

	struct drm_info_node *node = m->private;

	struct drm_device *dev = node->minor->dev;

	struct vc4_dev *vc4 = to_vc4_dev(dev);

	struct drm_printer p = drm_seq_file_printer(m);



	drm_printf(&p, "%d\n", atomic_read(&vc4->underrun));



	return 0;

}

#endif



/* The filter kernel is composed of dwords each containing 3 9-bit
@@ -166,6 +179,67 @@ static int vc4_hvs_upload_linear_kernel(struct vc4_hvs *hvs, 
	return 0;

}



void vc4_hvs_mask_underrun(struct drm_device *dev, int channel)

{

	struct vc4_dev *vc4 = to_vc4_dev(dev);

	u32 dispctrl = HVS_READ(SCALER_DISPCTRL);



	dispctrl &= ~SCALER_DISPCTRL_DSPEISLUR(channel);



	HVS_WRITE(SCALER_DISPCTRL, dispctrl);

}



void vc4_hvs_unmask_underrun(struct drm_device *dev, int channel)

{

	struct vc4_dev *vc4 = to_vc4_dev(dev);

	u32 dispctrl = HVS_READ(SCALER_DISPCTRL);



	dispctrl |= SCALER_DISPCTRL_DSPEISLUR(channel);



	HVS_WRITE(SCALER_DISPSTAT,

		  SCALER_DISPSTAT_EUFLOW(channel));

	HVS_WRITE(SCALER_DISPCTRL, dispctrl);

}



static void vc4_hvs_report_underrun(struct drm_device *dev)

{

	struct vc4_dev *vc4 = to_vc4_dev(dev);



	atomic_inc(&vc4->underrun);

	DRM_DEV_ERROR(dev->dev, "HVS underrun\n");

}



static irqreturn_t vc4_hvs_irq_handler(int irq, void *data)

{

	struct drm_device *dev = data;

	struct vc4_dev *vc4 = to_vc4_dev(dev);

	irqreturn_t irqret = IRQ_NONE;

	int channel;

	u32 control;

	u32 status;



	status = HVS_READ(SCALER_DISPSTAT);

	control = HVS_READ(SCALER_DISPCTRL);



	for (channel = 0; channel < SCALER_CHANNELS_COUNT; channel++) {

		/* Interrupt masking is not always honored, so check it here. */

		if (status & SCALER_DISPSTAT_EUFLOW(channel) &&

		    control & SCALER_DISPCTRL_DSPEISLUR(channel)) {

			vc4_hvs_mask_underrun(dev, channel);

			vc4_hvs_report_underrun(dev);



			irqret = IRQ_HANDLED;

		}

	}



	/* Clear every per-channel interrupt flag. */

	HVS_WRITE(SCALER_DISPSTAT, SCALER_DISPSTAT_IRQMASK(0) |

				   SCALER_DISPSTAT_IRQMASK(1) |

				   SCALER_DISPSTAT_IRQMASK(2));



	return irqret;

}



static int vc4_hvs_bind(struct device *dev, struct device *master, void *data)

{

	struct platform_device *pdev = to_platform_device(dev);
@@ -219,15 +293,36 @@ static int vc4_hvs_bind(struct device *dev, struct device *master, void *data) 
	dispctrl = HVS_READ(SCALER_DISPCTRL);



	dispctrl |= SCALER_DISPCTRL_ENABLE;

	dispctrl |= SCALER_DISPCTRL_DISPEIRQ(0) |

		    SCALER_DISPCTRL_DISPEIRQ(1) |

		    SCALER_DISPCTRL_DISPEIRQ(2);



	/* Set DSP3 (PV1) to use HVS channel 2, which would otherwise

	 * be unused.

	 */

	dispctrl &= ~SCALER_DISPCTRL_DSP3_MUX_MASK;

	dispctrl &= ~(SCALER_DISPCTRL_DMAEIRQ |

		      SCALER_DISPCTRL_SLVWREIRQ |

		      SCALER_DISPCTRL_SLVRDEIRQ |

		      SCALER_DISPCTRL_DSPEIEOF(0) |

		      SCALER_DISPCTRL_DSPEIEOF(1) |

		      SCALER_DISPCTRL_DSPEIEOF(2) |

		      SCALER_DISPCTRL_DSPEIEOLN(0) |

		      SCALER_DISPCTRL_DSPEIEOLN(1) |

		      SCALER_DISPCTRL_DSPEIEOLN(2) |

		      SCALER_DISPCTRL_DSPEISLUR(0) |

		      SCALER_DISPCTRL_DSPEISLUR(1) |

		      SCALER_DISPCTRL_DSPEISLUR(2) |

		      SCALER_DISPCTRL_SCLEIRQ);

	dispctrl |= VC4_SET_FIELD(2, SCALER_DISPCTRL_DSP3_MUX);



	HVS_WRITE(SCALER_DISPCTRL, dispctrl);



	ret = devm_request_irq(dev, platform_get_irq(pdev, 0),

			       vc4_hvs_irq_handler, 0, "vc4 hvs", drm);

	if (ret)

		return ret;



	return 0;

}

drivers/gpu/drm/vc4/vc4_kms.c

+10 −0
Original line number Diff line number Diff line
@@ -138,6 +138,16 @@ vc4_atomic_complete_commit(struct drm_atomic_state *state) 
{

	struct drm_device *dev = state->dev;

	struct vc4_dev *vc4 = to_vc4_dev(dev);

	struct vc4_crtc *vc4_crtc;

	int i;



	for (i = 0; i < dev->mode_config.num_crtc; i++) {

		if (!state->crtcs[i].ptr || !state->crtcs[i].commit)

			continue;



		vc4_crtc = to_vc4_crtc(state->crtcs[i].ptr);

		vc4_hvs_mask_underrun(dev, vc4_crtc->channel);

	}



	drm_atomic_helper_wait_for_fences(dev, state, false);