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Commit 52aee5bc authored by Hemant Kumar's avatar Hemant Kumar
Browse files

mhi: core: Add write_reg call back for mhi controller 



This allows to make a decision if different write call
back needs to be called.

Change-Id: I888da16e15e30ac1a7cb58d9272d6041b4d30ec7
Signed-off-by: default avatarHemant Kumar <hemantk@codeaurora.org>
parent 8edb589a

drivers/bus/mhi/core/mhi_boot.c

+15 −12
Original line number Original line Diff line number Diff line
@@ -158,13 +158,14 @@ void mhi_rddm_prepare(struct mhi_controller *mhi_cntrl, 




	MHI_LOG("BHIe programming for RDDM\n");

	MHI_LOG("BHIe programming for RDDM\n");





	mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS,

	mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECADDR_HIGH_OFFS,

		      upper_32_bits(mhi_buf->dma_addr));

		      upper_32_bits(mhi_buf->dma_addr));





	mhi_write_reg(mhi_cntrl, base, BHIE_RXVECADDR_LOW_OFFS,

	mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECADDR_LOW_OFFS,

		      lower_32_bits(mhi_buf->dma_addr));

		      lower_32_bits(mhi_buf->dma_addr));





	mhi_write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS, mhi_buf->len);

	mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_RXVECSIZE_OFFS,

			mhi_buf->len);

	sequence_id = prandom_u32() & BHIE_RXVECSTATUS_SEQNUM_BMSK;

	sequence_id = prandom_u32() & BHIE_RXVECSTATUS_SEQNUM_BMSK;





	if (unlikely(!sequence_id))

	if (unlikely(!sequence_id))
@@ -234,7 +235,7 @@ static int __mhi_download_rddm_in_panic(struct mhi_controller *mhi_cntrl) 
			/* Hardware reset; force device to enter rddm */

			/* Hardware reset; force device to enter rddm */

			MHI_LOG(

			MHI_LOG(

				"Did not enter RDDM, do a host req. reset\n");

				"Did not enter RDDM, do a host req. reset\n");

			mhi_write_reg(mhi_cntrl, mhi_cntrl->regs,

			mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->regs,

				      MHI_SOC_RESET_REQ_OFFSET,

				      MHI_SOC_RESET_REQ_OFFSET,

				      MHI_SOC_RESET_REQ);

				      MHI_SOC_RESET_REQ);

			udelay(delayus);

			udelay(delayus);
@@ -310,13 +311,14 @@ static int mhi_fw_load_amss(struct mhi_controller *mhi_cntrl, 




	MHI_LOG("Starting BHIe Programming\n");

	MHI_LOG("Starting BHIe Programming\n");





	mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS,

	mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECADDR_HIGH_OFFS,

		      upper_32_bits(mhi_buf->dma_addr));

		      upper_32_bits(mhi_buf->dma_addr));





	mhi_write_reg(mhi_cntrl, base, BHIE_TXVECADDR_LOW_OFFS,

	mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECADDR_LOW_OFFS,

		      lower_32_bits(mhi_buf->dma_addr));

		      lower_32_bits(mhi_buf->dma_addr));





	mhi_write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS, mhi_buf->len);

	mhi_cntrl->write_reg(mhi_cntrl, base, BHIE_TXVECSIZE_OFFS,

			mhi_buf->len);





	mhi_cntrl->sequence_id = prandom_u32() & BHIE_TXVECSTATUS_SEQNUM_BMSK;

	mhi_cntrl->sequence_id = prandom_u32() & BHIE_TXVECSTATUS_SEQNUM_BMSK;

	mhi_write_reg_field(mhi_cntrl, base, BHIE_TXVECDB_OFFS,

	mhi_write_reg_field(mhi_cntrl, base, BHIE_TXVECDB_OFFS,
@@ -374,14 +376,15 @@ static int mhi_fw_load_sbl(struct mhi_controller *mhi_cntrl, 
		goto invalid_pm_state;

		goto invalid_pm_state;

	}

	}





	mhi_write_reg(mhi_cntrl, base, BHI_STATUS, 0);

	mhi_cntrl->write_reg(mhi_cntrl, base, BHI_STATUS, 0);

	mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH,

	mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGADDR_HIGH,

		      upper_32_bits(dma_addr));

		      upper_32_bits(dma_addr));

	mhi_write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW,

	mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGADDR_LOW,

		      lower_32_bits(dma_addr));

		      lower_32_bits(dma_addr));

	mhi_write_reg(mhi_cntrl, base, BHI_IMGSIZE, size);

	mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGSIZE, size);

	mhi_cntrl->session_id = prandom_u32() & BHI_TXDB_SEQNUM_BMSK;

	mhi_cntrl->session_id = prandom_u32() & BHI_TXDB_SEQNUM_BMSK;

	mhi_write_reg(mhi_cntrl, base, BHI_IMGTXDB, mhi_cntrl->session_id);

	mhi_cntrl->write_reg(mhi_cntrl, base, BHI_IMGTXDB,

			mhi_cntrl->session_id);

	read_unlock_bh(pm_lock);

	read_unlock_bh(pm_lock);





	MHI_LOG("Waiting for image transfer completion\n");

	MHI_LOG("Waiting for image transfer completion\n");

drivers/bus/mhi/core/mhi_init.c

+5 −3
Original line number Original line Diff line number Diff line
@@ -684,7 +684,7 @@ static int mhi_init_bw_scale(struct mhi_controller *mhi_cntrl) 
	MHI_LOG("BW_CFG OFFSET:0x%x\n", bw_cfg_offset);

	MHI_LOG("BW_CFG OFFSET:0x%x\n", bw_cfg_offset);





	/* advertise host support */

	/* advertise host support */

	mhi_write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset,

	mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->regs, bw_cfg_offset,

		      MHI_BW_SCALE_SETUP(er_index));

		      MHI_BW_SCALE_SETUP(er_index));





	return 0;

	return 0;
@@ -782,8 +782,8 @@ int mhi_init_mmio(struct mhi_controller *mhi_cntrl) 




	/* setup wake db */

	/* setup wake db */

	mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);

	mhi_cntrl->wake_db = base + val + (8 * MHI_DEV_WAKE_DB);

	mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0);

	mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->wake_db, 4, 0);

	mhi_write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0);

	mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->wake_db, 0, 0);

	mhi_cntrl->wake_set = false;

	mhi_cntrl->wake_set = false;





	/* setup bw scale db */

	/* setup bw scale db */
@@ -1405,6 +1405,8 @@ int of_register_mhi_controller(struct mhi_controller *mhi_cntrl) 
		mhi_cntrl->unmap_single = mhi_unmap_single_no_bb;

		mhi_cntrl->unmap_single = mhi_unmap_single_no_bb;

	}

	}





	mhi_cntrl->write_reg = mhi_write_reg;



	/* read the device info if possible */

	/* read the device info if possible */

	if (mhi_cntrl->regs) {

	if (mhi_cntrl->regs) {

		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs,

		ret = mhi_read_reg(mhi_cntrl, mhi_cntrl->regs,

drivers/bus/mhi/core/mhi_main.c

+4 −4
Original line number Original line Diff line number Diff line
@@ -113,15 +113,15 @@ void mhi_write_reg_field(struct mhi_controller *mhi_cntrl, 




	tmp &= ~mask;

	tmp &= ~mask;

	tmp |= (val << shift);

	tmp |= (val << shift);

	mhi_write_reg(mhi_cntrl, base, offset, tmp);

	mhi_cntrl->write_reg(mhi_cntrl, base, offset, tmp);

}

}





void mhi_write_db(struct mhi_controller *mhi_cntrl,

void mhi_write_db(struct mhi_controller *mhi_cntrl,

		  void __iomem *db_addr,

		  void __iomem *db_addr,

		  dma_addr_t wp)

		  dma_addr_t wp)

{

{

	mhi_write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(wp));

	mhi_cntrl->write_reg(mhi_cntrl, db_addr, 4, upper_32_bits(wp));

	mhi_write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(wp));

	mhi_cntrl->write_reg(mhi_cntrl, db_addr, 0, lower_32_bits(wp));

}

}





void mhi_db_brstmode(struct mhi_controller *mhi_cntrl,

void mhi_db_brstmode(struct mhi_controller *mhi_cntrl,
@@ -1473,7 +1473,7 @@ int mhi_process_bw_scale_ev_ring(struct mhi_controller *mhi_cntrl, 




	read_lock_bh(&mhi_cntrl->pm_lock);

	read_lock_bh(&mhi_cntrl->pm_lock);

	if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)))

	if (likely(MHI_DB_ACCESS_VALID(mhi_cntrl)))

		mhi_write_reg(mhi_cntrl, mhi_cntrl->bw_scale_db, 0,

		mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->bw_scale_db, 0,

			      MHI_BW_SCALE_RESULT(result,

			      MHI_BW_SCALE_RESULT(result,

						  link_info.sequence_num));

						  link_info.sequence_num));

drivers/bus/mhi/core/mhi_pm.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -609,7 +609,7 @@ static void mhi_pm_disable_transition(struct mhi_controller *mhi_cntrl, 
		 * device cleares INTVEC as part of RESET processing,

		 * device cleares INTVEC as part of RESET processing,

		 * re-program it

		 * re-program it

		 */

		 */

		mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);

		mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);

	}

	}





	MHI_LOG("Waiting for all pending event ring processing to complete\n");

	MHI_LOG("Waiting for all pending event ring processing to complete\n");
@@ -932,7 +932,7 @@ int mhi_async_power_up(struct mhi_controller *mhi_cntrl) 
		mhi_cntrl->bhie = mhi_cntrl->regs + val;

		mhi_cntrl->bhie = mhi_cntrl->regs + val;

	}

	}





	mhi_write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);

	mhi_cntrl->write_reg(mhi_cntrl, mhi_cntrl->bhi, BHI_INTVEC, 0);

	mhi_cntrl->pm_state = MHI_PM_POR;

	mhi_cntrl->pm_state = MHI_PM_POR;

	mhi_cntrl->ee = MHI_EE_MAX;

	mhi_cntrl->ee = MHI_EE_MAX;

	current_ee = mhi_get_exec_env(mhi_cntrl);

	current_ee = mhi_get_exec_env(mhi_cntrl);

include/linux/mhi.h

+2 −0
Original line number Original line Diff line number Diff line
@@ -352,6 +352,8 @@ struct mhi_controller { 
	void (*tsync_log)(struct mhi_controller *mhi_cntrl, u64 remote_time);

	void (*tsync_log)(struct mhi_controller *mhi_cntrl, u64 remote_time);

	int (*bw_scale)(struct mhi_controller *mhi_cntrl,

	int (*bw_scale)(struct mhi_controller *mhi_cntrl,

			struct mhi_link_info *link_info);

			struct mhi_link_info *link_info);

	void (*write_reg)(struct mhi_controller *mhi_cntrl, void __iomem *base,

			u32 offset, u32 val);





	/* channel to control DTR messaging */

	/* channel to control DTR messaging */

	struct mhi_device *dtr_dev;

	struct mhi_device *dtr_dev;