Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 528c36e1 authored by Daniel Vetter's avatar Daniel Vetter Committed by Greg Kroah-Hartman
Browse files

radeon: insert 10ms sleep in dce5_crtc_load_lut 

[ Upstream commit ec3d65082d7dabad6fa8f66a8ef166f2d522d6b2 ]

Per at least one tester this is enough magic to recover the regression
introduced for some people (but not all) in

commit b8e2b019
Author: Peter Rosin <peda@axentia.se>
Date:   Tue Jul 4 12:36:57 2017 +0200

    drm/fb-helper: factor out pseudo-palette

which for radeon had the side-effect of refactoring out a seemingly
redudant writing of the color palette.

10ms in a fairly slow modeset path feels like an acceptable form of
duct-tape, so maybe worth a shot and see what sticks.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
References: https://bugzilla.kernel.org/show_bug.cgi?id=198123


Signed-off-by: default avatarDaniel Vetter <daniel.vetter@intel.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarSasha Levin <sashal@kernel.org>
parent 224c0751

drivers/gpu/drm/radeon/radeon_display.c

+2 −0
Original line number Original line Diff line number Diff line
@@ -127,6 +127,8 @@ static void dce5_crtc_load_lut(struct drm_crtc *crtc) 




	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);

	DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);





	msleep(10);



	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

	WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,

	       (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |

	       (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |

		NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));

		NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));