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Commit 52899b99 authored by Jerome Brunet's avatar Jerome Brunet Committed by Ulf Hansson
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mmc: meson-gx: clean up some constants 



Remove unused clock rate defines. These should not be defined but
requested from the clock framework.

Also correct typo on the DELAY register

Reviewed-by: default avatarKevin Hilman <khilman@baylibre.com>
Signed-off-by: default avatarJerome Brunet <jbrunet@baylibre.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 130b4bd8

drivers/mmc/host/meson-gx-mmc.c

+1 −3
Original line number Original line Diff line number Diff line
@@ -45,9 +45,7 @@ 
#define   CLK_DIV_MAX 63

#define   CLK_DIV_MAX 63

#define   CLK_SRC_MASK GENMASK(7, 6)

#define   CLK_SRC_MASK GENMASK(7, 6)

#define   CLK_SRC_XTAL 0   /* external crystal */

#define   CLK_SRC_XTAL 0   /* external crystal */

#define   CLK_SRC_XTAL_RATE 24000000

#define   CLK_SRC_PLL 1    /* FCLK_DIV2 */

#define   CLK_SRC_PLL 1    /* FCLK_DIV2 */

#define   CLK_SRC_PLL_RATE 1000000000

#define   CLK_CORE_PHASE_MASK GENMASK(9, 8)

#define   CLK_CORE_PHASE_MASK GENMASK(9, 8)

#define   CLK_TX_PHASE_MASK GENMASK(11, 10)

#define   CLK_TX_PHASE_MASK GENMASK(11, 10)

#define   CLK_RX_PHASE_MASK GENMASK(13, 12)

#define   CLK_RX_PHASE_MASK GENMASK(13, 12)
@@ -57,7 +55,7 @@ 
#define   CLK_PHASE_270 3

#define   CLK_PHASE_270 3

#define   CLK_ALWAYS_ON BIT(24)

#define   CLK_ALWAYS_ON BIT(24)





#define SD_EMMC_DElAY 0x4

#define SD_EMMC_DELAY 0x4

#define SD_EMMC_ADJUST 0x8

#define SD_EMMC_ADJUST 0x8

#define SD_EMMC_CALOUT 0x10

#define SD_EMMC_CALOUT 0x10

#define SD_EMMC_START 0x40

#define SD_EMMC_START 0x40