Commit 52592f9a authored Feb 27, 2022 by Taniya Das Committed by Greg Kroah-Hartman Apr 15, 2022

clk: qcom: clk-rcg2: Update logic to calculate D value for RCG



[ Upstream commit 58922910add18583d5273c2edcdb9fd7bf4eca02 ]

The display pixel clock has a requirement on certain newer platforms to
support M/N as (2/3) and the final D value calculated results in
underflow errors.
As the current implementation does not check for D value is within
the accepted range for a given M & N value. Update the logic to
calculate the final D value based on the range.

Fixes: 99cbd064 ("clk: qcom: Support display RCG clocks")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220227175536.3131-1-tdas@codeaurora.org


Signed-off-by: Sasha Levin <sashal@kernel.org>

parent b576488f

drivers/clk/qcom/clk-rcg2.c

+11 −2

Original line number	Diff line number	Diff line
		@@ -263,7 +263,7 @@ static int clk_rcg2_determine_floor_rate(struct clk_hw *hw,

		static int __clk_rcg2_configure(struct clk_rcg2 rcg, const struct freq_tbl f)
		{
		u32 cfg, mask;
		u32 cfg, mask, d_val, not2d_val, n_minus_m;
		struct clk_hw *hw = &rcg->clkr.hw;
		int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src);

		@@ -282,8 +282,17 @@ static int __clk_rcg2_configure(struct clk_rcg2 rcg, const struct freq_tbl f)
		if (ret)
		return ret;

		/* Calculate 2d value */
		d_val = f->n;

		n_minus_m = f->n - f->m;
		n_minus_m *= 2;

		d_val = clamp_t(u32, d_val, f->m, n_minus_m);
		not2d_val = ~d_val & mask;

		ret = regmap_update_bits(rcg->clkr.regmap,
		RCG_D_OFFSET(rcg), mask, ~f->n);
		RCG_D_OFFSET(rcg), mask, not2d_val);
		if (ret)
		return ret;
		}