Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 521c66c1 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "asoc: codecs: bolero: toggle zero gate for first hpf update"

parents 0098ac9c 144659b9

asoc/codecs/bolero/tx-macro.c

+7 −3
Original line number Diff line number Diff line
@@ -463,10 +463,10 @@ static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 
	snd_soc_component_update_bits(component,

			dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,

			hpf_cut_off_freq << 5);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x02);

	/* Minimum 1 clk cycle delay is required as per HW spec */

	usleep_range(1000, 1010);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x01);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00);

}



static void tx_macro_mute_update_callback(struct work_struct *work)
@@ -878,6 +878,10 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
			tx_vol_ctl_reg, 0x20, 0x20);

		snd_soc_component_update_bits(component,

			hpf_gate_reg, 0x01, 0x00);

		/*

		 * Minimum 1 clk cycle delay is required as per HW spec

		 */

		usleep_range(1000, 1010);



		hpf_cut_off_freq = (

			snd_soc_component_read32(component, dec_cfg_reg) &
@@ -900,7 +904,7 @@ static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, 
					&tx_priv->tx_hpf_work[decimator].dwork,

					msecs_to_jiffies(300));

			snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x02, 0x02);

					hpf_gate_reg, 0x03, 0x03);

			/*

			 * Minimum 1 clk cycle delay is required as per HW spec

			 */

asoc/codecs/bolero/va-macro.c

+7 −3
Original line number Diff line number Diff line
@@ -717,10 +717,10 @@ static void va_macro_tx_hpf_corner_freq_callback(struct work_struct *work) 
	snd_soc_component_update_bits(component,

			dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK,

			hpf_cut_off_freq << 5);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x02);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x02);

	/* Minimum 1 clk cycle delay is required as per HW spec */

	usleep_range(1000, 1010);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x03, 0x01);

	snd_soc_component_update_bits(component, hpf_gate_reg, 0x02, 0x00);

}



static void va_macro_mute_update_callback(struct work_struct *work)
@@ -1012,6 +1012,10 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
				tx_vol_ctl_reg, 0x20, 0x20);

		snd_soc_component_update_bits(component,

				hpf_gate_reg, 0x01, 0x00);

		/*

		 * Minimum 1 clk cycle delay is required as per HW spec

		 */

		usleep_range(1000, 1010);



		hpf_cut_off_freq = (snd_soc_component_read32(

					component, dec_cfg_reg) &
@@ -1024,7 +1028,7 @@ static int va_macro_enable_dec(struct snd_soc_dapm_widget *w, 
					    TX_HPF_CUT_OFF_FREQ_MASK,

					    CF_MIN_3DB_150HZ << 5);

			snd_soc_component_update_bits(component,

					hpf_gate_reg, 0x02, 0x02);

					hpf_gate_reg, 0x03, 0x03);

			/*

			 * Minimum 1 clk cycle delay is required as per HW spec

			 */