Merge "msm: kgsl: Update the IFPC power up reglist"

	A6XX_CP_AHB_CNTL,

};

/* Applicable to a620, a642l, a650 and a660 */

/* Applicable to a620, a642, a642l, a650 and a660 */

static u32 a650_ifpc_pwrup_reglist[] = {

	A6XX_CP_PROTECT_REG+32,

	A6XX_CP_PROTECT_REG+33,

	A6XX_CP_PROTECT_REG+34,

	A6XX_CP_PROTECT_REG+35,

	A6XX_CP_PROTECT_REG+36,

	A6XX_CP_PROTECT_REG+37,

	A6XX_CP_PROTECT_REG+38,

	A6XX_CP_PROTECT_REG+39,

	A6XX_CP_PROTECT_REG+40,

	A6XX_CP_PROTECT_REG+41,

	A6XX_CP_PROTECT_REG+42,

	A6XX_CP_PROTECT_REG+43,

	A6XX_CP_PROTECT_REG+44,

	A6XX_CP_PROTECT_REG+45,

	A6XX_CP_PROTECT_REG+46,

	A6XX_CP_PROTECT_REG+47,

};

/* Applicable to a620, a635, a650 and a660 */

static u32 a650_pwrup_reglist[] = {

	A6XX_CP_PROTECT_REG + 47,          /* Programmed for infinite span */

	A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,

static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev)

{

	struct a6xx_reglist_list reglist[3];

	struct a6xx_reglist_list reglist[4];

	void *ptr = adreno_dev->pwrup_reglist->hostptr;

	struct cpu_gpu_lock *lock = ptr;

	int items = 0, i, j;

	u32 *dest = ptr + sizeof(*lock);

	u16 list_offset = 0;

	/* Static IFPC-only registers */

	reglist[items++] = REGLIST(a6xx_ifpc_pwrup_reglist);

	reglist[items] = REGLIST(a6xx_ifpc_pwrup_reglist);

	list_offset += reglist[items++].count * 2;

	if (adreno_is_a650_family(adreno_dev)) {

		reglist[items] = REGLIST(a650_ifpc_pwrup_reglist);

		list_offset += reglist[items++].count * 2;

	}

	/* Static IFPC + preemption registers */

	reglist[items++] = REGLIST(a6xx_pwrup_reglist);

	 * all the lists and list_offset should be specified as the size in

	 * dwords of the first entry in the list.

	 */

	lock->list_offset = reglist[0].count * 2;

	lock->list_offset = list_offset;

}