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Commit 51f932b1 authored by Harshdeep Dhatt's avatar Harshdeep Dhatt
Browse files

msm: kgsl: Create a6xx rgmu power ops 



This completely dissociates the power sequences from
the kgsl power controller for rgmu based targets and
makes them target specific.

Change-Id: I7f848ab507762ee6cdcfa6f64d07c84967a35bfa
Signed-off-by: default avatarHarshdeep Dhatt <hdhatt@codeaurora.org>
parent cbb23004

drivers/gpu/msm/adreno-gpulist.h

+1 −1
Original line number Diff line number Diff line
@@ -1382,7 +1382,7 @@ static const struct adreno_a6xx_core adreno_gpu_core_a612 = { 
		.features = ADRENO_CONTENT_PROTECTION |

			ADRENO_IOCOHERENT | ADRENO_PREEMPTION | ADRENO_GPMU |

			ADRENO_IFPC,

		.gpudev = &adreno_a6xx_gpudev,

		.gpudev = &adreno_a6xx_rgmu_gpudev,

		.gmem_base = 0x100000,

		.gmem_size = (SZ_128K + SZ_4K),

		.bus_width = 32,

drivers/gpu/msm/adreno.h

+1 −0
Original line number Diff line number Diff line
@@ -906,6 +906,7 @@ extern struct adreno_gpudev adreno_a3xx_gpudev; 
extern struct adreno_gpudev adreno_a5xx_gpudev;

extern struct adreno_gpudev adreno_a6xx_gpudev;

extern struct adreno_gpudev adreno_a6xx_gmu_gpudev;

extern struct adreno_gpudev adreno_a6xx_rgmu_gpudev;



extern int adreno_wake_nice;

extern unsigned int adreno_wake_timeout;

drivers/gpu/msm/adreno_a6xx.c

+35 −0
Original line number Diff line number Diff line
@@ -2712,3 +2712,38 @@ struct adreno_gpudev adreno_a6xx_gmu_gpudev = { 
	.read_alwayson = a6xx_read_alwayson,

	.power_ops = &a6xx_gmu_power_ops,

};



struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {

	.reg_offsets = a6xx_register_offsets,

	.probe = a6xx_rgmu_device_probe,

	.start = a6xx_start,

	.snapshot = a6xx_snapshot,

	.init = a6xx_init,

	.irq_handler = a6xx_irq_handler,

	.rb_start = a6xx_rb_start,

	.regulator_enable = a6xx_sptprac_enable,

	.regulator_disable = a6xx_sptprac_disable,

	.perfcounters = &a6xx_perfcounters,

	.read_throttling_counters = a6xx_read_throttling_counters,

	.microcode_read = a6xx_microcode_read,

	.gpu_keepalive = a6xx_gpu_keepalive,

	.hw_isidle = a6xx_hw_isidle,

	.iommu_fault_block = a6xx_iommu_fault_block,

	.reset = a6xx_rgmu_restart,

	.preemption_pre_ibsubmit = a6xx_preemption_pre_ibsubmit,

	.preemption_post_ibsubmit = a6xx_preemption_post_ibsubmit,

	.preemption_init = a6xx_preemption_init,

	.preemption_schedule = a6xx_preemption_schedule,

	.set_marker = a6xx_set_marker,

	.preemption_context_init = a6xx_preemption_context_init,

	.preemption_context_destroy = a6xx_preemption_context_destroy,

	.sptprac_is_on = a6xx_sptprac_is_on,

	.ccu_invalidate = a6xx_ccu_invalidate,

	.perfcounter_update = a6xx_perfcounter_update,

#ifdef CONFIG_QCOM_KGSL_CORESIGHT

	.coresight = {&a6xx_coresight, &a6xx_coresight_cx},

#endif

	.clk_set_options = a6xx_clk_set_options,

	.read_alwayson = a6xx_read_alwayson,

	.power_ops = &a6xx_rgmu_power_ops,

};

drivers/gpu/msm/adreno_a6xx.h

+4 −0
Original line number Diff line number Diff line
@@ -11,8 +11,10 @@ 


#include "a6xx_reg.h"

#include "adreno_a6xx_gmu.h"

#include "adreno_a6xx_rgmu.h"



extern const struct adreno_power_ops a6xx_gmu_power_ops;

extern const struct adreno_power_ops a6xx_rgmu_power_ops;



/**

 * struct a6xx_device - Container for the a6xx_device
@@ -20,6 +22,8 @@ extern const struct adreno_power_ops a6xx_gmu_power_ops; 
struct a6xx_device {

	/** @gmu: Container for the a6xx GMU device */

	struct a6xx_gmu_device gmu;

	/** @rgmu: Container for the a6xx rGMU device */

	struct a6xx_rgmu_device rgmu;

	/** @adreno_dev: Container for the generic adreno device */

	struct adreno_device adreno_dev;

};

drivers/gpu/msm/adreno_a6xx_gmu.c

+6 −6
Original line number Diff line number Diff line
@@ -2706,7 +2706,7 @@ static int a6xx_gmu_power_off(struct adreno_device *adreno_dev) 
	return ret;

}



static void enable_gpu_irq(struct adreno_device *adreno_dev)

void a6xx_enable_gpu_irq(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;
@@ -2717,7 +2717,7 @@ static void enable_gpu_irq(struct adreno_device *adreno_dev) 
	trace_kgsl_irq(device, 1);

}



static void disable_gpu_irq(struct adreno_device *adreno_dev)

void a6xx_disable_gpu_irq(struct adreno_device *adreno_dev)

{

	struct kgsl_device *device = KGSL_DEVICE(adreno_dev);

	struct kgsl_pwrctrl *pwr = &device->pwrctrl;
@@ -2769,11 +2769,11 @@ static int a6xx_gpu_boot(struct adreno_device *adreno_dev) 
	/* Clear FSR here in case it is set from a previous pagefault */

	kgsl_mmu_clear_fsr(&device->mmu);



	enable_gpu_irq(adreno_dev);

	a6xx_enable_gpu_irq(adreno_dev);



	ret = a6xx_rb_start(adreno_dev);

	if (ret) {

		disable_gpu_irq(adreno_dev);

		a6xx_disable_gpu_irq(adreno_dev);

		goto oob_clear;

	}
@@ -2953,7 +2953,7 @@ static int a6xx_power_off(struct adreno_device *adreno_dev) 
	a6xx_gmu_oob_clear(device, oob_gpu);



no_gx_power:

	disable_gpu_irq(adreno_dev);

	a6xx_disable_gpu_irq(adreno_dev);



	a6xx_gmu_power_off(adreno_dev);
@@ -3157,7 +3157,7 @@ int a6xx_gmu_restart(struct kgsl_device *device) 


	a6xx_hfi_stop(adreno_dev);



	disable_gpu_irq(adreno_dev);

	a6xx_disable_gpu_irq(adreno_dev);



	/* Hard reset the gmu and gpu */

	a6xx_gmu_suspend(adreno_dev);