Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 518f6a54 authored by Alex Deucher's avatar Alex Deucher
Browse files

drm/amdgpu/powerplay: split out common smu9 BACO code 



Several of the BACO functions are common across smu9-based
asics.  Split the common code out.

Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 750cced1

drivers/gpu/drm/amd/powerplay/hwmgr/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -36,7 +36,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \ 
		pp_overdriver.o smu_helper.o \

		vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \

		vega20_thermal.o common_baco.o vega10_baco.o  vega20_baco.o \

		vega12_baco.o

		vega12_baco.o smu9_baco.o



AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR))

drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.c

0 → 100644
+66 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2018 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#include "amdgpu.h"

#include "soc15.h"

#include "soc15_hw_ip.h"

#include "vega10_ip_offset.h"

#include "soc15_common.h"

#include "vega10_inc.h"

#include "smu9_baco.h"



int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);

	uint32_t reg, data;



	*cap = false;

	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))

		return 0;



	WREG32(0x12074, 0xFFF0003B);

	data = RREG32(0x12075);



	if (data == 0x1) {

		reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);



		if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)

			*cap = true;

	}



	return 0;

}



int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);

	uint32_t reg;



	reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);



	if (reg & BACO_CNTL__BACO_MODE_MASK)

		/* gfx has already entered BACO state */

		*state = BACO_STATE_IN;

	else

		*state = BACO_STATE_OUT;

	return 0;

}

drivers/gpu/drm/amd/powerplay/hwmgr/smu9_baco.h

0 → 100644
+31 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2018 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 */

#ifndef __SMU9_BACO_H__

#define __SMU9_BACO_H__

#include "hwmgr.h"

#include "common_baco.h"



extern int smu9_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);

extern int smu9_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);



#endif

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.c

+1 −38
Original line number Diff line number Diff line
@@ -85,48 +85,11 @@ static const struct soc15_baco_cmd_entry clean_baco_tbl[] = 
	{CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0},

};



int vega10_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);

	uint32_t reg, data;



	*cap = false;

	if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO))

		return 0;



	WREG32(0x12074, 0xFFF0003B);

	data = RREG32(0x12075);



	if (data == 0x1) {

		reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0);



		if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK)

			*cap = true;

	}



	return 0;

}



int vega10_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state)

{

	struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev);

	uint32_t reg;



	reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL);



	if (reg & BACO_CNTL__BACO_MODE_MASK)

		/* gfx has already entered BACO state */

		*state = BACO_STATE_IN;

	else

		*state = BACO_STATE_OUT;

	return 0;

}



int vega10_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state)

{

	enum BACO_STATE cur_state;



	vega10_baco_get_state(hwmgr, &cur_state);

	smu9_baco_get_state(hwmgr, &cur_state);



	if (cur_state == state)

		/* aisc already in the target state */

drivers/gpu/drm/amd/powerplay/hwmgr/vega10_baco.h

+1 −4
Original line number Diff line number Diff line
@@ -22,11 +22,8 @@ 
 */

#ifndef __VEGA10_BACO_H__

#define __VEGA10_BACO_H__

#include "hwmgr.h"

#include "common_baco.h"

#include "smu9_baco.h"



extern int vega10_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap);

extern int vega10_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state);

extern int vega10_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state);



#endif