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Commit 5140512d authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'v4.20-rockchip-dts32-1' of... 

Merge tag 'v4.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

Nodes for the newly support rk3188 display controller, a fix for a new
dtc warning, gpio setting for the sdmmc regulator on radxarock and a
new board the "S" variant of the rk3288-based Tinker board, that sports
an added emmc.

* tag 'v4.20-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip

:
  ARM: dts: rockchip: add rk3288-based Tinker board S
  ARM: dts: rockchip: move shared tinker-board nodes to a common dtsi
  ARM: dts: rockchip: explicitly set vcc_sd0 pin to gpio on rk3188-radxarock
  ARM: dts: rockchip: Fix erroneous SPI bus dtc warnings on rk3036
  ARM: dts: rockchip: add rk3188 lcd controller nodes

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 22b92921 186b4565

Documentation/devicetree/bindings/arm/rockchip.txt

+4 −0
Original line number Diff line number Diff line
@@ -17,6 +17,10 @@ Rockchip platforms device tree bindings 
    Required root node properties:

      - compatible = "asus,rk3288-tinker", "rockchip,rk3288";



- Asus Tinker board S

    Required root node properties:

      - compatible = "asus,rk3288-tinker-s", "rockchip,rk3288";



- Kylin RK3036 board:

    Required root node properties:

      - compatible = "rockchip,kylin-rk3036", "rockchip,rk3036";

arch/arm/boot/dts/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -870,6 +870,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ 
	rk3288-r89.dtb \

	rk3288-rock2-square.dtb \

	rk3288-tinker.dtb \

	rk3288-tinker-s.dtb \

	rk3288-veyron-brain.dtb \

	rk3288-veyron-jaq.dtb \

	rk3288-veyron-jerry.dtb \

arch/arm/boot/dts/rk3036.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -733,7 +733,7 @@ 
			/* no rts / cts for uart2 */

		};



		spi {

		spi-pins {

			spi_txd:spi-txd {

				rockchip,pins = <1 29 RK_FUNC_3 &pcfg_pull_default>;

			};

arch/arm/boot/dts/rk3188-radxarock.dts

+8 −0
Original line number Diff line number Diff line
@@ -93,6 +93,8 @@ 
		regulator-min-microvolt = <3300000>;

		regulator-max-microvolt = <3300000>;

		gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_LOW>;

		pinctrl-names = "default";

		pinctrl-0 = <&sdmmc_pwr>;

		startup-delay-us = <100000>;

		vin-supply = <&vcc_io>;

	};
@@ -315,6 +317,12 @@ 
		};

	};



	sd0 {

		sdmmc_pwr: sdmmc-pwr {

			rockchip,pins = <RK_GPIO3 1 RK_FUNC_GPIO &pcfg_pull_none>;

		};

	};



	usb {

		host_vbus_drv: host-vbus-drv {

			rockchip,pins = <0 3 RK_FUNC_GPIO &pcfg_pull_none>;

arch/arm/boot/dts/rk3188.dtsi

+82 −0
Original line number Diff line number Diff line
@@ -56,6 +56,11 @@ 
		};

	};



	display-subsystem {

		compatible = "rockchip,display-subsystem";

		ports = <&vop0_out>, <&vop1_out>;

	};



	sram: sram@10080000 {

		compatible = "mmio-sram";

		reg = <0x10080000 0x8000>;
@@ -69,6 +74,38 @@ 
		};

	};



	vop0: vop@1010c000 {

		compatible = "rockchip,rk3188-vop";

		reg = <0x1010c000 0x1000>;

		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;

		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";

		resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;

		reset-names = "axi", "ahb", "dclk";

		status = "disabled";



		vop0_out: port {

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	vop1: vop@1010e000 {

		compatible = "rockchip,rk3188-vop";

		reg = <0x1010e000 0x1000>;

		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;

		clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;

		clock-names = "aclk_vop", "dclk_vop", "hclk_vop";

		resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;

		reset-names = "axi", "ahb", "dclk";

		status = "disabled";



		vop1_out: port {

			#address-cells = <1>;

			#size-cells = <0>;

		};

	};



	timer3: timer@2000e000 {

		compatible = "rockchip,rk3188-timer", "rockchip,rk3288-timer";

		reg = <0x2000e000 0x20>;
@@ -309,6 +346,51 @@ 
			};

		};



		lcdc1 {

			lcdc1_dclk: lcdc1-dclk {

				rockchip,pins = <2 RK_PD0 RK_FUNC_1 &pcfg_pull_none>;

			};



			lcdc1_den: lcdc1-den {

				rockchip,pins = <2 RK_PD1 RK_FUNC_1 &pcfg_pull_none>;

			};



			lcdc1_hsync: lcdc1-hsync {

				rockchip,pins = <2 RK_PD2 RK_FUNC_1 &pcfg_pull_none>;

			};



			lcdc1_vsync: lcdc1-vsync {

				rockchip,pins = <2 RK_PD3 RK_FUNC_1 &pcfg_pull_none>;

			};



			lcdc1_rgb24: ldcd1-rgb24 {

				rockchip,pins = <2 RK_PA0 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PA1 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PA2 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PA3 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PA4 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PA5 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PA6 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PA7 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PB0 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PB1 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PB2 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PB3 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PB4 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PB5 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PB6 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PB7 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PC0 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PC1 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PC2 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PC3 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PC4 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PC5 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PC6 RK_FUNC_1 &pcfg_pull_none>,

						<2 RK_PC7 RK_FUNC_1 &pcfg_pull_none>;

			};

		};



		pwm0 {

			pwm0_out: pwm0-out {

				rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_none>;