Loading qcom/msm-arm-smmu-lahaina.dtsi +44 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,15 @@ interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; qcom,actlr = /* All CBs of GFX: +15 deep PF */ <0x0 0x400 0x32B>, <0x1 0x400 0x32B>, <0x2 0x400 0x32B>, <0x4 0x400 0x32B>, <0x5 0x400 0x32B>, <0x7 0x400 0x32B>; interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, Loading Loading @@ -169,6 +178,41 @@ interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IMEM_CFG>; qcom,actlr = /* For HF-0 TBU +3 deep PF */ <0x800 0x3FF 0x103>, /* For HF-1 TBU +3 deep PF */ <0xC00 0x3FF 0x103>, /* For Compute-1 TBU +15 deep PF */ <0x1000 0x3FF 0x303>, /* For Compute-0 TBU +15 deep PF */ <0x1400 0x3FF 0x303>, /* For SF-[0/1] TBU Compute clients +15 deep PF */ <0x126 0x34C0 0x303>, <0x12D 0x24C0 0x303>, <0x144 0x2420 0x303>, <0x148 0x3420 0x303>, <0x149 0x34A0 0x303>, <0x14C 0x34A0 0x303>, <0x16F 0x3480 0x303>, <0x2142 0x4A0 0x303>, <0x2143 0x14A0 0x303>, <0x2147 0x420 0x303>, <0x2161 0x400 0x303>, <0x2165 0x480 0x303>, <0x216B 0x1400 0x303>, <0x216E 0x400 0x303>, /* For SF-[0/1] TBU Camera clients +3 deep PF */ <0x2000 0x4FF 0x103>, /* For SF-[0/1] TBU Video clients +3 deep PF */ <0x2100 0x403 0x103>, <0x2104 0x400 0x103>, /* For SF-[0/1] TBU CVP clients +3 deep PF */ <0x2120 0x403 0x103>, <0x2124 0x400 0x103>, /* For SF-[0/1] TBU Display clients +3 deep PF */ <0x215C 0x401 0x103>; anoc_1_tbu: anoc_1_tbu@15185000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15185000 0x1000>, Loading Loading
qcom/msm-arm-smmu-lahaina.dtsi +44 −0 Original line number Diff line number Diff line Loading @@ -25,6 +25,15 @@ interconnects = <&gem_noc MASTER_GPU_TCU &mc_virt SLAVE_EBI1>; qcom,actlr = /* All CBs of GFX: +15 deep PF */ <0x0 0x400 0x32B>, <0x1 0x400 0x32B>, <0x2 0x400 0x32B>, <0x4 0x400 0x32B>, <0x5 0x400 0x32B>, <0x7 0x400 0x32B>; interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, Loading Loading @@ -169,6 +178,41 @@ interconnects = <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IMEM_CFG>; qcom,actlr = /* For HF-0 TBU +3 deep PF */ <0x800 0x3FF 0x103>, /* For HF-1 TBU +3 deep PF */ <0xC00 0x3FF 0x103>, /* For Compute-1 TBU +15 deep PF */ <0x1000 0x3FF 0x303>, /* For Compute-0 TBU +15 deep PF */ <0x1400 0x3FF 0x303>, /* For SF-[0/1] TBU Compute clients +15 deep PF */ <0x126 0x34C0 0x303>, <0x12D 0x24C0 0x303>, <0x144 0x2420 0x303>, <0x148 0x3420 0x303>, <0x149 0x34A0 0x303>, <0x14C 0x34A0 0x303>, <0x16F 0x3480 0x303>, <0x2142 0x4A0 0x303>, <0x2143 0x14A0 0x303>, <0x2147 0x420 0x303>, <0x2161 0x400 0x303>, <0x2165 0x480 0x303>, <0x216B 0x1400 0x303>, <0x216E 0x400 0x303>, /* For SF-[0/1] TBU Camera clients +3 deep PF */ <0x2000 0x4FF 0x103>, /* For SF-[0/1] TBU Video clients +3 deep PF */ <0x2100 0x403 0x103>, <0x2104 0x400 0x103>, /* For SF-[0/1] TBU CVP clients +3 deep PF */ <0x2120 0x403 0x103>, <0x2124 0x400 0x103>, /* For SF-[0/1] TBU Display clients +3 deep PF */ <0x215C 0x401 0x103>; anoc_1_tbu: anoc_1_tbu@15185000 { compatible = "qcom,qsmmuv500-tbu"; reg = <0x15185000 0x1000>, Loading