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Commit 506a7be9 authored by Anson Huang's avatar Anson Huang Committed by Daniel Lezcano
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clocksource/drivers/imx-tpm: Correct some registers operation flow 



According to i.MX7ULP reference manual, TPM_SC_CPWMS can ONLY be written when
counter is disabled, TPM_SC_TOF is write-1-clear, TPM_C0SC_CHF is also
write-1-clear, correct these registers initialization flow;

Signed-off-by: default avatarAnson Huang <Anson.Huang@nxp.com>
Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
parent 16328e7b

drivers/clocksource/timer-imx-tpm.c

+7 −1
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#define TPM_SC				0x10

#define TPM_SC_CMOD_INC_PER_CNT		(0x1 << 3)

#define TPM_SC_CMOD_DIV_DEFAULT		0x3

#define TPM_SC_TOF_MASK			(0x1 << 7)

#define TPM_CNT				0x14

#define TPM_MOD				0x18

#define TPM_STATUS			0x1c
@@ -29,6 +30,7 @@ 
#define TPM_C0SC_MODE_SHIFT		2

#define TPM_C0SC_MODE_MASK		0x3c

#define TPM_C0SC_MODE_SW_COMPARE	0x4

#define TPM_C0SC_CHF_MASK		(0x1 << 7)

#define TPM_C0V				0x24



static void __iomem *timer_base;
@@ -205,9 +207,13 @@ static int __init tpm_timer_init(struct device_node *np) 
	 * 4) Channel0 disabled

	 * 5) DMA transfers disabled

	 */

	/* make sure counter is disabled */

	writel(0, timer_base + TPM_SC);

	/* TOF is W1C */

	writel(TPM_SC_TOF_MASK, timer_base + TPM_SC);

	writel(0, timer_base + TPM_CNT);

	writel(0, timer_base + TPM_C0SC);

	/* CHF is W1C */

	writel(TPM_C0SC_CHF_MASK, timer_base + TPM_C0SC);



	/* increase per cnt, div 8 by default */

	writel(TPM_SC_CMOD_INC_PER_CNT | TPM_SC_CMOD_DIV_DEFAULT,