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Commit 504fe96b authored by Paras Sharma's avatar Paras Sharma Committed by Gerrit - the friendly Code Review server
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ARM: dts: msm: Add QUPv3_0 and SE5 dt nodes for YUPIK 

Add QUPv3_0 device tree change for console UART on yupik.

Change-Id: I9d0af197eda7c784aea127a5cc8848674d3c81fa
parent 0bd22990

qcom/yupik-pinctrl.dtsi

+28 −0
Original line number Diff line number Diff line
@@ -8,5 +8,33 @@ 
		interrupt-controller;

		#interrupt-cells = <2>;

		wakeup-parent = <&pdc>;



		qupv3_se5_2uart_pins: qupv3_se5_2uart_pins {

			qupv3_se5_2uart_active: qupv3_se5_2uart_active {

				mux {

					pins = "gpio22", "gpio23";

					function = "qup05";

				};



				config {

					pins = "gpio22", "gpio23";

					drive-strength = <2>;

					bias-disable;

				};

			};



			qupv3_se5_2uart_sleep: qupv3_se5_2uart_sleep {

				mux {

					pins = "gpio22", "gpio23";

					function = "gpio";

				};



				config {

					pins = "gpio22", "gpio23";

					drive-strength = <2>;

					bias-pull-down;

				};

			};

		};

	};

};

qcom/yupik-qupv3.dtsi

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+35 −0
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#include <dt-bindings/interconnect/qcom,yupik.h>



&soc {

	/* QUPv3_0 wrapper instance */

	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {

		compatible = "qcom,qupv3-geni-se";

		reg = <0x9c0000 0x2000>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-bus-ids =

			<MASTER_QUP_CORE_0 SLAVE_QUP_CORE_0>,

			<MASTER_QUP_0 SLAVE_EBI1>;

		iommus = <&apps_smmu 0x123 0x0>;

		qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;

		qcom,iommu-geometry = <0x40000000 0x10000000>;

		qcom,iommu-dma = "fastmap";

		status = "ok";

	};



	/* Debug UART Instance */

	qupv3_se5_2uart: qcom,qup_uart@994000 {

		compatible = "qcom,msm-geni-console";

		reg = <0x994000 0x4000>;

		reg-names = "se_phys";

		interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;

		clock-names = "se-clk", "m-ahb", "s-ahb";

		clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,

			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se5_2uart_active>;

		pinctrl-1 = <&qupv3_se5_2uart_sleep>;

		qcom,wrapper-core = <&qupv3_0>;

		status = "ok";

	};

};

qcom/yupik-rumi.dtsi

+5 −0
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@@ -70,3 +70,8 @@ 


	status = "ok";

};



/* Debug UART console */

&qupv3_se5_2uart {

	qcom,rumi_platform;

};

qcom/yupik.dtsi

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@@ -1269,3 +1269,4 @@ 


#include "yupik-usb.dtsi"

#include "msm-arm-smmu-yupik.dtsi"

#include "yupik-qupv3.dtsi"