Commit 4fae9279 authored Jan 12, 2019 by John Hubbard Committed by Kishon Vijay Abraham I Jan 16, 2019

phy: fix build breakage: add PHY_MODE_SATA

Commit 49e54187 ("ata: libahci_platform: comply to PHY framework") uses
the PHY_MODE_SATA, but that enum had not yet been added. This caused a
build failure for me, with today's linux.git.

Also, there is a potentially conflicting (mis-named) PHY_MODE_SATA, hiding
in the Marvell Berlin SATA PHY driver.

Fix the build by:

    1) Renaming Marvell's defined value to a more scoped name,
       in order to avoid any potential conflicts: PHY_BERLIN_MODE_SATA.

    2) Adding the missing enum, which was going to be added anyway as part
       of [1].

[1] https://lkml.kernel.org/r/20190108163124.6409-3-miquel.raynal@bootlin.com



Fixes: 49e54187 ("ata: libahci_platform: comply to PHY framework")

Cc: Grzegorz Jaszczyk <jaz@semihalf.com>
Cc: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Jens Axboe <axboe@kernel.dk>
Signed-off-by: John Hubbard <jhubbard@nvidia.com>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

parent 1138a442

drivers/phy/marvell/phy-berlin-sata.c

+3 −2

Original line number	Diff line number	Diff line
		@@ -32,7 +32,7 @@

		/* register 0x01 */
		#define REF_FREF_SEL_25 BIT(0)
		#define PHY_MODE_SATA (0x0 << 5)
		#define PHY_BERLIN_MODE_SATA (0x0 << 5)

		/* register 0x02 */
		#define USE_MAX_PLL_RATE BIT(12)
		@@ -102,7 +102,8 @@ static int phy_berlin_sata_power_on(struct phy *phy)

		/* set PHY mode and ref freq to 25 MHz */
		phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x01,
		0x00ff, REF_FREF_SEL_25 \| PHY_MODE_SATA);
		0x00ff,
		REF_FREF_SEL_25 \| PHY_BERLIN_MODE_SATA);

		/* set PHY up to 6 Gbps */
		phy_berlin_sata_reg_setbits(ctrl_reg, priv->phy_base, 0x25,

include/linux/phy/phy.h

+1 −0

Original line number	Diff line number	Diff line
		@@ -42,6 +42,7 @@ enum phy_mode {
		PHY_MODE_PCIE,
		PHY_MODE_ETHERNET,
		PHY_MODE_MIPI_DPHY,
		PHY_MODE_SATA
		};

		/**