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Commit 4fa849d4 authored by Tom Lendacky's avatar Tom Lendacky Committed by Greg Kroah-Hartman
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x86/cpu: Add VM page flush MSR availablility as a CPUID feature 



commit 69372cf01290b9587d2cee8fbe161d75d55c3adc upstream.

On systems that do not have hardware enforced cache coherency between
encrypted and unencrypted mappings of the same physical page, the
hypervisor can use the VM page flush MSR (0xc001011e) to flush the cache
contents of an SEV guest page. When a small number of pages are being
flushed, this can be used in place of issuing a WBINVD across all CPUs.

CPUID 0x8000001f_eax[2] is used to determine if the VM page flush MSR is
available. Add a CPUID feature to indicate it is supported and define the
MSR.

Signed-off-by: default avatarTom Lendacky <thomas.lendacky@amd.com>
Message-Id: <f1966379e31f9b208db5257509c4a089a87d33d0.1607620209.git.thomas.lendacky@amd.com>
Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 998eec06

arch/x86/include/asm/cpufeatures.h

+1 −0
Original line number Diff line number Diff line
@@ -236,6 +236,7 @@ 
#define X86_FEATURE_VMCALL		( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */

#define X86_FEATURE_VMW_VMMCALL		( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */

#define X86_FEATURE_SEV_ES		( 8*32+20) /* AMD Secure Encrypted Virtualization - Encrypted State */

#define X86_FEATURE_VM_PAGE_FLUSH	( 8*32+21) /* "" VM Page Flush MSR is supported */



/* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */

#define X86_FEATURE_FSGSBASE		( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -495,6 +495,7 @@ 
#define MSR_AMD64_ICIBSEXTDCTL		0xc001103c

#define MSR_AMD64_IBSOPDATA4		0xc001103d

#define MSR_AMD64_IBS_REG_COUNT_MAX	8 /* includes MSR_AMD64_IBSBRTARGET */

#define MSR_AMD64_VM_PAGE_FLUSH		0xc001011e

#define MSR_AMD64_SEV			0xc0010131

#define MSR_AMD64_SEV_ENABLED_BIT	0

#define MSR_AMD64_SEV_ENABLED		BIT_ULL(MSR_AMD64_SEV_ENABLED_BIT)

arch/x86/kernel/cpu/scattered.c

+1 −0
Original line number Diff line number Diff line
@@ -44,6 +44,7 @@ static const struct cpuid_bit cpuid_bits[] = { 
	{ X86_FEATURE_SEV,		CPUID_EAX,  1, 0x8000001f, 0 },

	{ X86_FEATURE_SEV_ES,		CPUID_EAX,  3, 0x8000001f, 0 },

	{ X86_FEATURE_SME_COHERENT,	CPUID_EAX, 10, 0x8000001f, 0 },

	{ X86_FEATURE_VM_PAGE_FLUSH,	CPUID_EAX,  2, 0x8000001f, 0 },

	{ 0, 0, 0, 0, 0 }

};