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Commit 4f125084 authored by Deepak Kumar's avatar Deepak Kumar
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msm: kgsl: Drive FAL QACTIVE signal high before GMU boot 



Drive FAL QACTIVE signal high before GMU boot to make sure
path to DDR accepts transactions from GMU/GPU and comes out
of low power state if it was in a low power state.

Change-Id: I238a39c5b9dbd10a8c9b2c6437aaf48df410802f
Signed-off-by: default avatarDeepak Kumar <dkumar@codeaurora.org>
parent 488de248

drivers/gpu/msm/a6xx_reg.h

+1 −0
Original line number Diff line number Diff line
@@ -1039,6 +1039,7 @@ 


/* FAL10 veto register */

#define A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF         0x1F8F0

#define A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF     0x1F8F1



#define A6XX_GMU_AO_INTERRUPT_EN		0x23B03

#define A6XX_GMU_AO_HOST_INTERRUPT_CLR		0x23B04

drivers/gpu/msm/adreno_a6xx_gmu.c

+4 −1
Original line number Diff line number Diff line
@@ -1300,8 +1300,11 @@ static void a6xx_gmu_register_config(struct adreno_device *adreno_dev) 
	u32 gmu_log_info, chipid = 0;



	/* Vote veto for FAL10 feature if supported*/

	if (a6xx_core->veto_fal10)

	if (a6xx_core->veto_fal10) {

		gmu_core_regwrite(device, A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 0x1);

		gmu_core_regwrite(device,

			A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 0x1);

	}



	/* Turn on TCM retention */

	gmu_core_regwrite(device, A6XX_GMU_GENERAL_7, 1);