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Commit 4efd3460 authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'drm-fixes-2018-11-16' of git://anongit.freedesktop.org/drm/drm 

Pull drm fixes from Dave Airlie:
 "Live from Vancouver, SoC maintainer talk, this weeks drm fixes pull
  for rc3:

  omapdrm:
   - regression fixes for the reordering bridge stuff that went into rc1

  i915:
   - incorrect EU count fix
   - HPD storm fix
   - MST fix
   - relocation fix for gen4/5

  amdgpu:
   - huge page handling fix
   - IH ring setup
   - XGMI aperture setup
   - watermark setup fix

  misc:
   - docs and MST fix"

* tag 'drm-fixes-2018-11-16' of git://anongit.freedesktop.org/drm/drm: (23 commits)
  drm/i915: Account for scale factor when calculating initial phase
  drm/i915: Clean up skl_program_scaler()
  drm/i915: Move programming plane scaler to its own function.
  drm/i915/icl: Drop spurious register read from icl_dbuf_slices_update
  drm/i915: fix broadwell EU computation
  drm/amdgpu: fix huge page handling on Vega10
  drm/amd/pp: Fix truncated clock value when set watermark
  drm/amdgpu: fix bug with IH ring setup
  drm/meson: venc: dmt mode must use encp
  drm/amdgpu: set system aperture to cover whole FB region
  drm/i915: Fix hpd handling for pins with two encoders
  drm/i915/execlists: Force write serialisation into context image vs execution
  drm/i915/icl: Fix power well 2 wrt. DC-off toggling order
  drm/i915: Fix NULL deref when re-enabling HPD IRQs on systems with MST
  drm/i915: Fix possible race in intel_dp_add_mst_connector()
  drm/i915/ringbuffer: Delay after EMIT_INVALIDATE for gen4/gen5
  drm/omap: dsi: Fix missing of_platform_depopulate()
  drm/omap: Move DISPC runtime PM handling to omapdrm
  drm/omap: dsi: Ensure the device is active during probe
  drm/omap: hdmi4: Ensure the device is active during bind
  ...
parents ef268de1 20325e8a

arch/arm/mach-omap2/display.c

+53 −58
Original line number Diff line number Diff line
@@ -209,11 +209,61 @@ static int __init omapdss_init_fbdev(void) 


	return 0;

}

#else

static inline int omapdss_init_fbdev(void)



static const char * const omapdss_compat_names[] __initconst = {

	"ti,omap2-dss",

	"ti,omap3-dss",

	"ti,omap4-dss",

	"ti,omap5-dss",

	"ti,dra7-dss",

};



static struct device_node * __init omapdss_find_dss_of_node(void)

{

	struct device_node *node;

	int i;



	for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {

		node = of_find_compatible_node(NULL, NULL,

			omapdss_compat_names[i]);

		if (node)

			return node;

	}



	return NULL;

}



static int __init omapdss_init_of(void)

{

	int r;

	struct device_node *node;

	struct platform_device *pdev;



	/* only create dss helper devices if dss is enabled in the .dts */



	node = omapdss_find_dss_of_node();

	if (!node)

		return 0;



	if (!of_device_is_available(node))

		return 0;



	pdev = of_find_device_by_node(node);



	if (!pdev) {

		pr_err("Unable to find DSS platform device\n");

		return -ENODEV;

	}



	r = of_platform_populate(node, NULL, NULL, &pdev->dev);

	if (r) {

		pr_err("Unable to populate DSS submodule devices\n");

		return r;

	}



	return omapdss_init_fbdev();

}

omap_device_initcall(omapdss_init_of);

#endif /* CONFIG_FB_OMAP2 */



static void dispc_disable_outputs(void)
@@ -361,58 +411,3 @@ int omap_dss_reset(struct omap_hwmod *oh) 


	return r;

}
 


static const char * const omapdss_compat_names[] __initconst = {

	"ti,omap2-dss",

	"ti,omap3-dss",

	"ti,omap4-dss",

	"ti,omap5-dss",

	"ti,dra7-dss",

};



static struct device_node * __init omapdss_find_dss_of_node(void)

{

	struct device_node *node;

	int i;



	for (i = 0; i < ARRAY_SIZE(omapdss_compat_names); ++i) {

		node = of_find_compatible_node(NULL, NULL,

			omapdss_compat_names[i]);

		if (node)

			return node;

	}



	return NULL;

}



static int __init omapdss_init_of(void)

{

	int r;

	struct device_node *node;

	struct platform_device *pdev;



	/* only create dss helper devices if dss is enabled in the .dts */



	node = omapdss_find_dss_of_node();

	if (!node)

		return 0;



	if (!of_device_is_available(node))

		return 0;



	pdev = of_find_device_by_node(node);



	if (!pdev) {

		pr_err("Unable to find DSS platform device\n");

		return -ENODEV;

	}



	r = of_platform_populate(node, NULL, NULL, &pdev->dev);

	if (r) {

		pr_err("Unable to populate DSS submodule devices\n");

		return r;

	}



	return omapdss_init_fbdev();

}

omap_device_initcall(omapdss_init_of);

drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c

+10 −8
Original line number Diff line number Diff line
@@ -1632,13 +1632,6 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, 
			continue;

		}



		/* First check if the entry is already handled */

		if (cursor.pfn < frag_start) {

			cursor.entry->huge = true;

			amdgpu_vm_pt_next(adev, &cursor);

			continue;

		}



		/* If it isn't already handled it can't be a huge page */

		if (cursor.entry->huge) {

			/* Add the entry to the relocated list to update it. */
@@ -1701,10 +1694,19 @@ static int amdgpu_vm_update_ptes(struct amdgpu_pte_update_params *params, 
			}

		} while (frag_start < entry_end);



		if (frag >= shift)

		if (amdgpu_vm_pt_descendant(adev, &cursor)) {

			/* Mark all child entries as huge */

			while (cursor.pfn < frag_start) {

				cursor.entry->huge = true;

				amdgpu_vm_pt_next(adev, &cursor);

			}



		} else if (frag >= shift) {

			/* or just move on to the next on the same level. */

			amdgpu_vm_pt_next(adev, &cursor);

		}

	}



	return 0;

}

drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

+3 −3
Original line number Diff line number Diff line
@@ -72,7 +72,7 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 


	/* Program the system aperture low logical page number. */

	WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,

		     min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);

		     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);



	if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)

		/*
@@ -82,11 +82,11 @@ static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 
		 * to get rid of the VM fault and hardware hang.

		 */

		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			     max((adev->gmc.vram_end >> 18) + 0x1,

			     max((adev->gmc.fb_end >> 18) + 0x1,

				 adev->gmc.agp_end >> 18));

	else

		WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			     max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);

			     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



	/* Set default page address. */

	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start

drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c

+3 −3
Original line number Diff line number Diff line
@@ -90,7 +90,7 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 


	/* Program the system aperture low logical page number. */

	WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,

		     min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);

		     min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);



	if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)

		/*
@@ -100,11 +100,11 @@ static void mmhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev) 
		 * to get rid of the VM fault and hardware hang.

		 */

		WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			     max((adev->gmc.vram_end >> 18) + 0x1,

			     max((adev->gmc.fb_end >> 18) + 0x1,

				 adev->gmc.agp_end >> 18));

	else

		WREG32_SOC15(MMHUB, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,

			     max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);

			     max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);



	/* Set default page address. */

	value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +

drivers/gpu/drm/amd/amdgpu/vega10_ih.c

+1 −1
Original line number Diff line number Diff line
@@ -129,7 +129,7 @@ static int vega10_ih_irq_init(struct amdgpu_device *adev) 
	else

		wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFFFF);



	/* set rptr, wptr to 0 */

	WREG32_SOC15(OSSSYS, 0, mmIH_RB_RPTR, 0);