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Commit 4e6a32e6 authored by Arnd Bergmann's avatar Arnd Bergmann
Browse files

Merge tag 'mvebu-dt64-4.20-2' of git://git.infradead.org/linux-mvebu into next/dt

mvebu dt64 for 4.20 (part 2)

 - Add System Error Interrupt support to Armada SoCs (7K/8K)
 - Add CPU idle support on Armada 8K

* tag 'mvebu-dt64-4.20-2' of git://git.infradead.org/linux-mvebu

:
  arm64: dts: clearfog-gt-8k: add PCIe slot description
  arm64: dts: marvell: add CP110 ICU SEI subnode
  arm64: dts: marvell: use new bindings for CP110 interrupts
  arm64: dts: marvell: add AP806 SEI subnode
  arm64: dts: marvell: add CPU Idle power state support on Armada 7K/8K
  arm64: dts: marvell: Add node labels for the cpus

Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents 38764692 91f84690
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+1 −1
Original line number Diff line number Diff line
@@ -16,7 +16,7 @@
	compatible = "marvell,armada3720", "marvell,armada3710";

	cpus {
		cpu@1 {
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a53","arm,armv8";
			reg = <0x1>;
+1 −1
Original line number Diff line number Diff line
@@ -40,7 +40,7 @@
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		cpu@0 {
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a53", "arm,armv8";
			reg = <0>;
+7 −0
Original line number Diff line number Diff line
@@ -233,6 +233,13 @@
	};
};

&cp0_pcie0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_pci0_reset_pins>;
	reset-gpios = <&cp0_gpio2 0 GPIO_ACTIVE_LOW>;
	status = "okay";
};

&cp0_gpio2 {
	sata_reset {
		gpio-hog;
+2 −2
Original line number Diff line number Diff line
@@ -15,13 +15,13 @@
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x000>;
			enable-method = "psci";
		};
		cpu@1 {
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x001>;
+8 −4
Original line number Diff line number Diff line
@@ -15,29 +15,33 @@
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
		cpu0: cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x000>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
		};
		cpu@1 {
		cpu1: cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x001>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
		};
		cpu@100 {
		cpu2: cpu@100 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x100>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
		};
		cpu@101 {
		cpu3: cpu@101 {
			device_type = "cpu";
			compatible = "arm,cortex-a72", "arm,armv8";
			reg = <0x101>;
			enable-method = "psci";
			cpu-idle-states = <&CPU_SLEEP_0>;
		};
	};
};
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