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Commit 4e0f1229 authored by Sowjanya Komatineni's avatar Sowjanya Komatineni Committed by Thierry Reding
Browse files

arm64: tegra: Add SDMMC auto-calibration settings



Add SDMMC initial pad offsets used by auto calibration process.

Add SDMMC fixed drive strengths for Tegra210, Tegra186 and
Tegra194 which are used when calibration timeouts.

Fixed drive strengths are based on Pre SI Analysis of the pads.

Signed-off-by: default avatarSowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: default avatarThierry Reding <treding@nvidia.com>
parent 6ab6a4d2
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+2 −0
Original line number Diff line number Diff line
@@ -315,6 +315,8 @@
		nvidia,pad-autocal-pull-down-offset-hs400 = <0x05>;
		nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
		nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
		nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
		nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
		nvidia,default-tap = <0x5>;
		nvidia,default-trim = <0x9>;
		nvidia,dqs-trim = <63>;
+34 −0
Original line number Diff line number Diff line
@@ -303,6 +303,17 @@
			clock-names = "sdhci";
			resets = <&bpmp TEGRA194_RESET_SDMMC1>;
			reset-names = "sdhci";
			nvidia,pad-autocal-pull-up-offset-3v3-timeout =
									<0x07>;
			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
									<0x07>;
			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
									<0x07>;
			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
			nvidia,default-tap = <0x9>;
			nvidia,default-trim = <0x5>;
			status = "disabled";
		};

@@ -314,6 +325,18 @@
			clock-names = "sdhci";
			resets = <&bpmp TEGRA194_RESET_SDMMC3>;
			reset-names = "sdhci";
			nvidia,pad-autocal-pull-up-offset-1v8 = <0x00>;
			nvidia,pad-autocal-pull-down-offset-1v8 = <0x7a>;
			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
									<0x07>;
			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
									<0x07>;
			nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
			nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
			nvidia,default-tap = <0x9>;
			nvidia,default-trim = <0x5>;
			status = "disabled";
		};

@@ -325,6 +348,17 @@
			clock-names = "sdhci";
			resets = <&bpmp TEGRA194_RESET_SDMMC4>;
			reset-names = "sdhci";
			nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
			nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
			nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
			nvidia,pad-autocal-pull-down-offset-1v8-timeout =
									<0x0a>;
			nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
			nvidia,pad-autocal-pull-down-offset-3v3-timeout =
									<0x0a>;
			nvidia,default-tap = <0x8>;
			nvidia,default-trim = <0x14>;
			nvidia,dqs-trim = <40>;
			status = "disabled";
		};

+55 −2
Original line number Diff line number Diff line
@@ -477,6 +477,48 @@
		compatible = "nvidia,tegra210-pinmux";
		reg = <0x0 0x700008d4 0x0 0x29c>, /* Pad control registers */
		      <0x0 0x70003000 0x0 0x294>; /* Mux registers */
		sdmmc1_3v3_drv: sdmmc1-3v3-drv {
			sdmmc1 {
				nvidia,pins = "drive_sdmmc1";
				nvidia,pull-down-strength = <0x8>;
				nvidia,pull-up-strength = <0x8>;
			};
		};
		sdmmc1_1v8_drv: sdmmc1-1v8-drv {
			sdmmc1 {
				nvidia,pins = "drive_sdmmc1";
				nvidia,pull-down-strength = <0x4>;
				nvidia,pull-up-strength = <0x3>;
			};
		};
		sdmmc2_1v8_drv: sdmmc2-1v8-drv {
			sdmmc2 {
				nvidia,pins = "drive_sdmmc2";
				nvidia,pull-down-strength = <0x10>;
				nvidia,pull-up-strength = <0x10>;
			};
		};
		sdmmc3_3v3_drv: sdmmc3-3v3-drv {
			sdmmc3 {
				nvidia,pins = "drive_sdmmc3";
				nvidia,pull-down-strength = <0x8>;
				nvidia,pull-up-strength = <0x8>;
			};
		};
		sdmmc3_1v8_drv: sdmmc3-1v8-drv {
			sdmmc3 {
				nvidia,pins = "drive_sdmmc3";
				nvidia,pull-down-strength = <0x4>;
				nvidia,pull-up-strength = <0x3>;
			};
		};
		sdmmc4_1v8_drv: sdmmc4-1v8-drv {
			sdmmc4 {
				nvidia,pins = "drive_sdmmc4";
				nvidia,pull-down-strength = <0x10>;
				nvidia,pull-up-strength = <0x10>;
			};
		};
	};

	/*
@@ -1051,9 +1093,12 @@
		clock-names = "sdhci";
		resets = <&tegra_car 14>;
		reset-names = "sdhci";
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
				"sdmmc-3v3-drv", "sdmmc-1v8-drv";
		pinctrl-0 = <&sdmmc1_3v3>;
		pinctrl-1 = <&sdmmc1_1v8>;
		pinctrl-2 = <&sdmmc1_3v3_drv>;
		pinctrl-3 = <&sdmmc1_1v8_drv>;
		nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
		nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
		nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
@@ -1076,6 +1121,8 @@
		clock-names = "sdhci";
		resets = <&tegra_car 9>;
		reset-names = "sdhci";
		pinctrl-names = "sdmmc-1v8-drv";
		pinctrl-0 = <&sdmmc2_1v8_drv>;
		nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
		nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
		nvidia,default-tap = <0x8>;
@@ -1091,9 +1138,12 @@
		clock-names = "sdhci";
		resets = <&tegra_car 69>;
		reset-names = "sdhci";
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8";
		pinctrl-names = "sdmmc-3v3", "sdmmc-1v8",
				"sdmmc-3v3-drv", "sdmmc-1v8-drv";
		pinctrl-0 = <&sdmmc3_3v3>;
		pinctrl-1 = <&sdmmc3_1v8>;
		pinctrl-2 = <&sdmmc3_3v3_drv>;
		pinctrl-3 = <&sdmmc3_1v8_drv>;
		nvidia,pad-autocal-pull-up-offset-3v3 = <0x00>;
		nvidia,pad-autocal-pull-down-offset-3v3 = <0x7d>;
		nvidia,pad-autocal-pull-up-offset-1v8 = <0x7b>;
@@ -1111,6 +1161,9 @@
		clock-names = "sdhci";
		resets = <&tegra_car 15>;
		reset-names = "sdhci";
		pinctrl-names = "sdmmc-3v3-drv", "sdmmc-1v8-drv";
		pinctrl-0 = <&sdmmc4_1v8_drv>;
		pinctrl-1 = <&sdmmc4_1v8_drv>;
		nvidia,pad-autocal-pull-up-offset-1v8 = <0x05>;
		nvidia,pad-autocal-pull-down-offset-1v8 = <0x05>;
		nvidia,default-tap = <0x8>;