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Commit 4df64c3e authored by John Rigby's avatar John Rigby Committed by Grant Likely
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powerpc/mpc5121: Update device tree for MPC5121ADS evaluation board 



Current device tree is only bare bones.  This patch adds nodes to make
it a complete tree for the MPC5121ads.

Added nodes include:
    mbx      - opengl coprocessor
    nfc      - nand flash controller
    cpld-pic - on board cpld
    rtc
    clock    - clock control
    pmc      - power management control
    gpio
    mscan    - can module
    i2c
    axe      - audio coprocessor
    display  - display interface unit
    mdio
    ethernet
    usb
    ioctl    - pin config
    pata
    ac97     - PSC configured as AC97
    pscfifo  - psc fifo configuration
    dma
    pci

Fix typo in header changing MDS to ADS.

Add a compatible property of the form "fsl,mpc5121-..."
to nodes missing one.

Changed localbus compatible to fsl,mpc5121-localbus, this does
not break anything because the only code that uses it finds it
via the node name, not compatible.

Signed-off-by: default avatarJohn Rigby <jrigby@freescale.com>
Signed-off-by: default avatarGrant Likely <grant.likely@secretlab.ca>
parent 08b6c06d

arch/powerpc/boot/dts/mpc5121ads.dts

+299 −11
Original line number Original line Diff line number Diff line 
/*

/*

 * MPC5121E MDS Device Tree Source

 * MPC5121E ADS Device Tree Source

 *

 *

 * Copyright 2007 Freescale Semiconductor Inc.

 * Copyright 2007,2008 Freescale Semiconductor Inc.

 *

 *

 * This program is free software; you can redistribute  it and/or modify it

 * This program is free software; you can redistribute  it and/or modify it

 * under  the terms of  the GNU General  Public License as published by the

 * under  the terms of  the GNU General  Public License as published by the
@@ -17,6 +17,10 @@ 
	#address-cells = <1>;

	#address-cells = <1>;

	#size-cells = <1>;

	#size-cells = <1>;





	aliases {

		pci = &pci;

	};



	cpus {

	cpus {

		#address-cells = <1>;

		#address-cells = <1>;

		#size-cells = <0>;

		#size-cells = <0>;
@@ -39,8 +43,41 @@ 
		reg = <0x00000000 0x10000000>;	// 256MB at 0

		reg = <0x00000000 0x10000000>;	// 256MB at 0

	};

	};





	mbx@20000000 {

		compatible = "fsl,mpc5121-mbx";

		reg = <0x20000000 0x4000>;

		interrupts = <66 0x8>;

		interrupt-parent = < &ipic >;

	};



	sram@30000000 {

		compatible = "fsl,mpc5121-sram";

		reg = <0x30000000 0x20000>;		// 128K at 0x30000000

	};



	nfc@40000000 {

		compatible = "fsl,mpc5121-nfc";

		reg = <0x40000000 0x100000>;	// 1M at 0x40000000

		interrupts = <6 8>;

		interrupt-parent = < &ipic >;

		#address-cells = <1>;

		#size-cells = <1>;

		bank-width = <1>;

		// ADS has two Hynix 512MB Nand flash chips in a single

		// stacked package .

		chips = <2>;

		nand0@0 {

			label = "nand0";

			reg = <0x00000000 0x02000000>; 	// first 32 MB of chip 0

		};

		nand1@20000000 {

			label = "nand1";

			reg = <0x20000000 0x02000000>; 	// first 32 MB of chip 1

		};

	};



	localbus@80000020 {

	localbus@80000020 {

		compatible = "fsl,mpc5121ads-localbus";

		compatible = "fsl,mpc5121-localbus";

		#address-cells = <2>;

		#address-cells = <2>;

		#size-cells = <1>;

		#size-cells = <1>;

		reg = <0x80000020 0x40>;

		reg = <0x80000020 0x40>;
@@ -51,14 +88,51 @@ 
		flash@0,0 {

		flash@0,0 {

			compatible = "cfi-flash";

			compatible = "cfi-flash";

			reg = <0 0x0 0x4000000>;

			reg = <0 0x0 0x4000000>;

			#address-cells = <1>;

			#size-cells = <1>;

			bank-width = <4>;

			bank-width = <4>;

			device-width = <1>;

			device-width = <2>;

			protected@0 {

				label = "protected";

				reg = <0x00000000 0x00040000>;  // first sector is protected

				read-only;

			};

			filesystem@40000 {

				label = "filesystem";

				reg = <0x00040000 0x03c00000>;  // 60M for filesystem

			};

			kernel@3c40000 {

				label = "kernel";

				reg = <0x03c40000 0x00280000>;  // 2.5M for kernel

			};

			device-tree@3ec0000 {

				label = "device-tree";

				reg = <0x03ec0000 0x00040000>;  // one sector for device tree

			};

			u-boot@3f00000 {

				label = "u-boot";

				reg = <0x03f00000 0x00100000>;  // 1M for u-boot

				read-only;

			};

		};

		};





		board-control@2,0 {

		board-control@2,0 {

			compatible = "fsl,mpc5121ads-cpld";

			compatible = "fsl,mpc5121ads-cpld";

			reg = <0x2 0x0 0x8000>;

			reg = <0x2 0x0 0x8000>;

		};

		};



		cpld_pic: pic@2,a {

			compatible = "fsl,mpc5121ads-cpld-pic";

			interrupt-controller;

			#interrupt-cells = <2>;

			reg = <0x2 0xa 0x5>;

			interrupt-parent = < &ipic >;

			// irq routing

			//	all irqs but touch screen are routed to irq0 (ipic 48)

			//	touch screen is statically routed to irq1 (ipic 17)

			//	so don't use it here

			interrupts = <48 0x8>;

		};

	};

	};





	soc@80000000 {

	soc@80000000 {
@@ -85,38 +159,252 @@ 
			reg = <0xc00 0x100>;

			reg = <0xc00 0x100>;

		};

		};





		// 512x PSCs are not 52xx PSCs compatible

		rtc@a00 {	// Real time clock

			compatible = "fsl,mpc5121-rtc";

			reg = <0xa00 0x100>;

			interrupts = <79 0x8 80 0x8>;

			interrupt-parent = < &ipic >;

		};



		clock@f00 {	// Clock control

			compatible = "fsl,mpc5121-clock";

			reg = <0xf00 0x100>;

		};



		pmc@1000{  //Power Management Controller

			compatible = "fsl,mpc5121-pmc";

			reg = <0x1000 0x100>;

			interrupts = <83 0x2>;

			interrupt-parent = < &ipic >;

		};



		gpio@1100 {

			compatible = "fsl,mpc5121-gpio";

			reg = <0x1100 0x100>;

			interrupts = <78 0x8>;

			interrupt-parent = < &ipic >;

		};



		mscan@1300 {

			compatible = "fsl,mpc5121-mscan";

			cell-index = <0>;

			interrupts = <12 0x8>;

			interrupt-parent = < &ipic >;

			reg = <0x1300 0x80>;

		};



		mscan@1380 {

			compatible = "fsl,mpc5121-mscan";

			cell-index = <1>;

			interrupts = <13 0x8>;

			interrupt-parent = < &ipic >;

			reg = <0x1380 0x80>;

		};



		i2c@1700 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			cell-index = <0>;

			reg = <0x1700 0x20>;

			interrupts = <9 0x8>;

			interrupt-parent = < &ipic >;

			fsl5200-clocking;

		};



		i2c@1720 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			cell-index = <1>;

			reg = <0x1720 0x20>;

			interrupts = <10 0x8>;

			interrupt-parent = < &ipic >;

			fsl5200-clocking;

		};



		i2c@1740 {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "fsl,mpc5121-i2c", "fsl-i2c";

			cell-index = <2>;

			reg = <0x1740 0x20>;

			interrupts = <11 0x8>;

			interrupt-parent = < &ipic >;

			fsl5200-clocking;

		};



		i2ccontrol@1760 {

			compatible = "fsl,mpc5121-i2c-ctrl";

			reg = <0x1760 0x8>;

		};



		axe@2000 {

			compatible = "fsl,mpc5121-axe";

			reg = <0x2000 0x100>;

			interrupts = <42 0x8>;

			interrupt-parent = < &ipic >;

		};



		display@2100 {

			compatible = "fsl,mpc5121-diu", "fsl-diu";

			reg = <0x2100 0x100>;

			interrupts = <64 0x8>;

			interrupt-parent = < &ipic >;

		};



		mdio@2800 {

			compatible = "fsl,mpc5121-fec-mdio";

			reg = <0x2800 0x800>;

			#address-cells = <1>;

			#size-cells = <0>;

			phy: ethernet-phy@0 {

				reg = <1>;

				device_type = "ethernet-phy";

			};

		};



		ethernet@2800 {

			device_type = "network";

			compatible = "fsl,mpc5121-fec";

			reg = <0x2800 0x800>;

			local-mac-address = [ 00 00 00 00 00 00 ];

			interrupts = <4 0x8>;

			interrupt-parent = < &ipic >;

			phy-handle = < &phy >;

			fsl,align-tx-packets = <4>;

		};



		// 5121e has two dr usb modules

		// mpc5121_ads only uses USB0



		// USB1 using external ULPI PHY

		//usb@3000 {

		//	compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";

		//	reg = <0x3000 0x1000>;

		//	#address-cells = <1>;

		//	#size-cells = <0>;

		//	interrupt-parent = < &ipic >;

		//	interrupts = <43 0x8>;

		//	dr_mode = "otg";

		//	phy_type = "ulpi";

		//	port1;

		//};



		// USB0 using internal UTMI PHY

		usb@4000 {

			compatible = "fsl,mpc5121-usb2-dr", "fsl-usb2-dr";

			reg = <0x4000 0x1000>;

			#address-cells = <1>;

			#size-cells = <0>;

			interrupt-parent = < &ipic >;

			interrupts = <44 0x8>;

			dr_mode = "otg";

			phy_type = "utmi_wide";

			port0;

		};



		// IO control

		ioctl@a000 {

			compatible = "fsl,mpc5121-ioctl";

			reg = <0xA000 0x1000>;

		};



		pata@10200 {

			compatible = "fsl,mpc5121-pata";

			reg = <0x10200 0x100>;

			interrupts = <5 0x8>;

			interrupt-parent = < &ipic >;

		};



		// 512x PSCs are not 52xx PSC compatible

		// PSC3 serial port A aka ttyPSC0

		// PSC3 serial port A aka ttyPSC0

		serial@11300 {

		serial@11300 {

			device_type = "serial";

			device_type = "serial";

			compatible = "fsl,mpc5121-psc-uart";

			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";

			// Logical port assignment needed until driver

			// Logical port assignment needed until driver

			// learns to use aliases

			// learns to use aliases

			port-number = <0>;

			port-number = <0>;

			cell-index = <3>;

			cell-index = <3>;

			reg = <0x11300 0x100>;

			reg = <0x11300 0x100>;

			interrupts = <0x28 0x8>; // actually the fifo irq

			interrupts = <40 0x8>;

			interrupt-parent = < &ipic >;

			interrupt-parent = < &ipic >;

			rx-fifo-size = <16>;

			tx-fifo-size = <16>;

		};

		};





		// PSC4 serial port B aka ttyPSC1

		// PSC4 serial port B aka ttyPSC1

		serial@11400 {

		serial@11400 {

			device_type = "serial";

			device_type = "serial";

			compatible = "fsl,mpc5121-psc-uart";

			compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";

			// Logical port assignment needed until driver

			// Logical port assignment needed until driver

			// learns to use aliases

			// learns to use aliases

			port-number = <1>;

			port-number = <1>;

			cell-index = <4>;

			cell-index = <4>;

			reg = <0x11400 0x100>;

			reg = <0x11400 0x100>;

			interrupts = <0x28 0x8>; // actually the fifo irq

			interrupts = <40 0x8>;

			interrupt-parent = < &ipic >;

			interrupt-parent = < &ipic >;

			rx-fifo-size = <16>;

			tx-fifo-size = <16>;

		};

		};





		pscsfifo@11f00 {

		// PSC5 in ac97 mode

		ac97@11500 {

			compatible = "fsl,mpc5121-psc-ac97", "fsl,mpc5121-psc";

			cell-index = <5>;

			reg = <0x11500 0x100>;

			interrupts = <40 0x8>;

			interrupt-parent = < &ipic >;

			fsl,mode = "ac97-slave";

			rx-fifo-size = <384>;

			tx-fifo-size = <384>;

		};



		pscfifo@11f00 {

			compatible = "fsl,mpc5121-psc-fifo";

			compatible = "fsl,mpc5121-psc-fifo";

			reg = <0x11f00 0x100>;

			reg = <0x11f00 0x100>;

			interrupts = <0x28 0x8>;

			interrupts = <40 0x8>;

			interrupt-parent = < &ipic >;

		};



		dma@14000 {

			compatible = "fsl,mpc5121-dma2";

			reg = <0x14000 0x1800>;

			interrupts = <65 0x8>;

			interrupt-parent = < &ipic >;

			interrupt-parent = < &ipic >;

		};

		};



	};



	pci: pci@80008500 {

		interrupt-map-mask = <0xf800 0x0 0x0 0x7>;

		interrupt-map = <

				// IDSEL 0x15 - Slot 1 PCI

				 0xa800 0x0 0x0 0x1 &cpld_pic 0x0 0x8

				 0xa800 0x0 0x0 0x2 &cpld_pic 0x1 0x8

				 0xa800 0x0 0x0 0x3 &cpld_pic 0x2 0x8

				 0xa800 0x0 0x0 0x4 &cpld_pic 0x3 0x8



				// IDSEL 0x16 - Slot 2 MiniPCI

				 0xb000 0x0 0x0 0x1 &cpld_pic 0x4 0x8

				 0xb000 0x0 0x0 0x2 &cpld_pic 0x5 0x8



				// IDSEL 0x17 - Slot 3 MiniPCI

				 0xb800 0x0 0x0 0x1 &cpld_pic 0x6 0x8

				 0xb800 0x0 0x0 0x2 &cpld_pic 0x7 0x8

				>;

		interrupt-parent = < &ipic >;

		interrupts = <1 0x8>;

		bus-range = <0 0>;

		ranges = <0x42000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000

			  0x02000000 0x0 0xb0000000 0xb0000000 0x0 0x10000000

			  0x01000000 0x0 0x00000000 0x84000000 0x0 0x01000000>;

		clock-frequency = <0>;

		#interrupt-cells = <1>;

		#size-cells = <2>;

		#address-cells = <3>;

		reg = <0x80008500 0x100>;

		compatible = "fsl,mpc5121-pci";

		device_type = "pci";

	};

	};

};
 
};