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Commit 4db11c37 authored by Douglas Anderson's avatar Douglas Anderson Committed by Heiko Stuebner
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ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron 



This is the other half of the hacky solution from commit f497ab6b
("ARM: dts: rockchip: Configure BT_HOST_WAKE as wake-up signal on
veyron").  Specifically the LPM driver that the Broadcom Bluetooth
expects to have (but is missing in mainline) has two halves of the
equation: BT_HOST_WAKE and BT_DEV_WAKE.  The BT_HOST_WAKE (which was
handled in the previous commit) is the one that lets the Bluetooth
wake the system up.  The BT_DEV_WAKE (this patch) tells the Bluetooth
that it's OK to go into a low power mode.  That means we were burning
a bit of extra power in S3 without this patch.  Measurements are a bit
noisy, but it appears to be a few mA worth of difference.

NOTE: Though these pins don't do much on systems with Marvell
Bluetooth, downstream kernels set it on all veyron boards so we'll do
the same.

Signed-off-by: default avatarDouglas Anderson <dianders@chromium.org>
Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
parent f497ab6b

arch/arm/boot/dts/rk3288-veyron-chromebook.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -237,6 +237,7 @@ 


		/* Wake only */

		&suspend_l_wake

		&bt_dev_wake_awake

	>;

	pinctrl-1 = <

		/* Common for sleep and wake, but no owners */
@@ -246,6 +247,7 @@ 


		/* Sleep only */

		&suspend_l_sleep

		&bt_dev_wake_sleep

	>;



	backlight {

arch/arm/boot/dts/rk3288-veyron.dtsi

+20 −0
Original line number Diff line number Diff line
@@ -485,12 +485,18 @@ 
		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff



		/* Wake only */

		&bt_dev_wake_awake

	>;

	pinctrl-1 = <

		/* Common for sleep and wake, but no owners */

		&ddr0_retention

		&ddrio_pwroff

		&global_pwroff



		/* Sleep only */

		&bt_dev_wake_sleep

	>;



	pcfg_pull_none_drv_8ma: pcfg-pull-none-drv-8ma {
@@ -596,6 +602,20 @@ 
		sdio0_clk: sdio0-clk {

			rockchip,pins = <4 RK_PD1 1 &pcfg_pull_none_drv_8ma>;

		};



		/*

		 * These pins are only present on very new veyron boards; on

		 * older boards bt_dev_wake is simply always high.  Note that

		 * gpio4_D2 is a NC on old veyron boards, so it doesn't hurt

		 * to map this pin everywhere

		 */

		bt_dev_wake_sleep: bt-dev-wake-sleep {

			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_low>;

		};



		bt_dev_wake_awake: bt-dev-wake-awake {

			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_output_high>;

		};

	};



	tpm {