Loading drivers/clk/qcom/gcc-shima.c +5 −5 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ #include <linux/clk.h> Loading Loading @@ -1099,7 +1099,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .name = "gcc_sdcc1_apps_clk_src", .parent_data = gcc_parent_data_7, .num_parents = 6, .ops = &clk_rcg2_ops, .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, Loading Loading @@ -1128,7 +1128,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parent_data_1, .num_parents = 5, .ops = &clk_rcg2_ops, .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, Loading Loading @@ -1161,7 +1161,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_8, .num_parents = 7, .ops = &clk_rcg2_ops, .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, Loading Loading @@ -1192,7 +1192,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .name = "gcc_sdcc4_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = 5, .ops = &clk_rcg2_ops, .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, Loading Loading
drivers/clk/qcom/gcc-shima.c +5 −5 Original line number Diff line number Diff line // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2020, The Linux Foundation. All rights reserved. * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. */ #include <linux/clk.h> Loading Loading @@ -1099,7 +1099,7 @@ static struct clk_rcg2 gcc_sdcc1_apps_clk_src = { .name = "gcc_sdcc1_apps_clk_src", .parent_data = gcc_parent_data_7, .num_parents = 6, .ops = &clk_rcg2_ops, .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, Loading Loading @@ -1128,7 +1128,7 @@ static struct clk_rcg2 gcc_sdcc1_ice_core_clk_src = { .name = "gcc_sdcc1_ice_core_clk_src", .parent_data = gcc_parent_data_1, .num_parents = 5, .ops = &clk_rcg2_ops, .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, Loading Loading @@ -1161,7 +1161,7 @@ static struct clk_rcg2 gcc_sdcc2_apps_clk_src = { .name = "gcc_sdcc2_apps_clk_src", .parent_data = gcc_parent_data_8, .num_parents = 7, .ops = &clk_rcg2_ops, .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, Loading Loading @@ -1192,7 +1192,7 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = { .name = "gcc_sdcc4_apps_clk_src", .parent_data = gcc_parent_data_1, .num_parents = 5, .ops = &clk_rcg2_ops, .ops = &clk_rcg2_floor_ops, }, .clkr.vdd_data = { .vdd_class = &vdd_cx, Loading