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Commit 4d8d44c6 authored by Rex Zhu's avatar Rex Zhu Committed by Alex Deucher
Browse files

drm/amd/powerplay: refine code to avoid potential bug that the memory not cleared. 



Signed-off-by: default avatarRex Zhu <Rex.Zhu@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 31bb90f1

drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

+7 −10
Original line number Original line Diff line number Diff line
@@ -4398,16 +4398,14 @@ static int smu7_get_sclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 
		if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)

		if (table_info == NULL || table_info->vdd_dep_on_sclk == NULL)

			return -EINVAL;

			return -EINVAL;

		dep_sclk_table = table_info->vdd_dep_on_sclk;

		dep_sclk_table = table_info->vdd_dep_on_sclk;

		for (i = 0; i < dep_sclk_table->count; i++) {

		for (i = 0; i < dep_sclk_table->count; i++)

			clocks->clock[i] = dep_sclk_table->entries[i].clk;

			clocks->clock[i] = dep_sclk_table->entries[i].clk;

			clocks->count++;

		clocks->count = dep_sclk_table->count;

		}

	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {

	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {

		sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;

		sclk_table = hwmgr->dyn_state.vddc_dependency_on_sclk;

		for (i = 0; i < sclk_table->count; i++) {

		for (i = 0; i < sclk_table->count; i++)

			clocks->clock[i] = sclk_table->entries[i].clk;

			clocks->clock[i] = sclk_table->entries[i].clk;

			clocks->count++;

		clocks->count = sclk_table->count;

		}

	}

	}





	return 0;

	return 0;
@@ -4441,14 +4439,13 @@ static int smu7_get_mclks(struct pp_hwmgr *hwmgr, struct amd_pp_clocks *clocks) 
			clocks->clock[i] = dep_mclk_table->entries[i].clk;

			clocks->clock[i] = dep_mclk_table->entries[i].clk;

			clocks->latency[i] = smu7_get_mem_latency(hwmgr,

			clocks->latency[i] = smu7_get_mem_latency(hwmgr,

						dep_mclk_table->entries[i].clk);

						dep_mclk_table->entries[i].clk);

			clocks->count++;

		}

		}

		clocks->count = dep_mclk_table->count;

	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {

	} else if (hwmgr->pp_table_version == PP_TABLE_V0) {

		mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;

		mclk_table = hwmgr->dyn_state.vddc_dependency_on_mclk;

		for (i = 0; i < mclk_table->count; i++) {

		for (i = 0; i < mclk_table->count; i++)

			clocks->clock[i] = mclk_table->entries[i].clk;

			clocks->clock[i] = mclk_table->entries[i].clk;

			clocks->count++;

		clocks->count = mclk_table->count;

		}

	}

	}

	return 0;

	return 0;

}

}