Loading qcom/lahaina.dtsi +7 −3 Original line number Diff line number Diff line Loading @@ -556,9 +556,13 @@ #reset-cells = <1>; }; clock_dispcc: qcom,dispcc { compatible = "qcom,dummycc"; clock-output-names = "dispcc_clocks"; clock_dispcc: qcom,dispcc@af00000 { compatible = "qcom,lahaina-dispcc", "syscon"; reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; clock-names = "cfg_ahb_clk"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; #clock-cells = <1>; #reset-cells = <1>; }; Loading Loading
qcom/lahaina.dtsi +7 −3 Original line number Diff line number Diff line Loading @@ -556,9 +556,13 @@ #reset-cells = <1>; }; clock_dispcc: qcom,dispcc { compatible = "qcom,dummycc"; clock-output-names = "dispcc_clocks"; clock_dispcc: qcom,dispcc@af00000 { compatible = "qcom,lahaina-dispcc", "syscon"; reg = <0xaf00000 0x20000>; reg-name = "cc_base"; vdd_mm-supply = <&VDD_MM_LEVEL>; clock-names = "cfg_ahb_clk"; clocks = <&clock_gcc GCC_DISP_AHB_CLK>; #clock-cells = <1>; #reset-cells = <1>; }; Loading