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Commit 4d52b2ac authored by Boris Brezillon's avatar Boris Brezillon Committed by Michael Turquette
Browse files

clk: mvebu: add missing CESA gate clk 



Even if not documented in the datasheet, the Armada 370 SoC can actually
gate the CESA (crypto engine) clock.
Add an entry in the gating_desc table to be able to reference the CESA
gateclk in the crypto node.

Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: default avatarGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: default avatarMichael Turquette <mturquette@linaro.org>
parent 5343325f

Documentation/devicetree/bindings/clock/mvebu-gated-clock.txt

+1 −0
Original line number Diff line number Diff line
@@ -19,6 +19,7 @@ ID Clock Peripheral 
9	pex1	PCIe Cntrl 1

15	sata0	SATA Host 0

17	sdio	SDHCI Host

23	crypto	CESA (crypto engine)

25	tdm	Time Division Mplx

28	ddr	DDR Cntrl

30	sata1	SATA Host 0

drivers/clk/mvebu/armada-370.c

+1 −0
Original line number Diff line number Diff line
@@ -163,6 +163,7 @@ static const struct clk_gating_soc_desc a370_gating_desc[] __initconst = { 
	{ "pex1", "pex1_en", 9, 0 },

	{ "sata0", NULL, 15, 0 },

	{ "sdio", NULL, 17, 0 },

	{ "crypto", NULL, 23, 0 },

	{ "tdm", NULL, 25, 0 },

	{ "ddr", NULL, 28, CLK_IGNORE_UNUSED },

	{ "sata1", NULL, 30, 0 },