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Commit 4d47d640 authored by Kan Liang's avatar Kan Liang Committed by Ingo Molnar
Browse files

perf/x86/intel/uncore: Support CoffeeLake 8th CBOX 



Coffee Lake has 8 core products which has 8 Cboxes. The 8th CBOX is
mapped into different MSR space.

Increase the num_boxes to 8 to handle the new products. It will not
impact the previous platforms, SkyLake, KabyLake and earlier CoffeeLake.
Because the num_boxes will be recalculated in uncore_cpu_init and
doesn't exceed the x86_max_cores.

Introduce a new box flag bit to indicate the 8th CBOX.

Signed-off-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarPeter Zijlstra (Intel) <peterz@infradead.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/20181019170419.378-2-kan.liang@linux.intel.com


Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
parent c10a8de0

arch/x86/events/intel/uncore.h

+25 −8
Original line number Diff line number Diff line
@@ -129,8 +129,15 @@ struct intel_uncore_box { 
	struct intel_uncore_extra_reg shared_regs[0];

};



/* CFL uncore 8th cbox MSRs */

#define CFL_UNC_CBO_7_PERFEVTSEL0		0xf70

#define CFL_UNC_CBO_7_PER_CTR0			0xf76



#define UNCORE_BOX_FLAG_INITIATED		0

#define UNCORE_BOX_FLAG_CTL_OFFS8	1 /* event config registers are 8-byte apart */

/* event config registers are 8-byte apart */

#define UNCORE_BOX_FLAG_CTL_OFFS8		1

/* CFL 8th CBOX has different MSR space */

#define UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS	2



struct uncore_event_desc {

	struct kobj_attribute attr;
@@ -297,18 +304,28 @@ unsigned int uncore_freerunning_counter(struct intel_uncore_box *box, 
static inline

unsigned uncore_msr_event_ctl(struct intel_uncore_box *box, int idx)

{

	if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {

		return CFL_UNC_CBO_7_PERFEVTSEL0 +

		       (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);

	} else {

		return box->pmu->type->event_ctl +

		       (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +

		       uncore_msr_box_offset(box);

	}

}



static inline

unsigned uncore_msr_perf_ctr(struct intel_uncore_box *box, int idx)

{

	if (test_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags)) {

		return CFL_UNC_CBO_7_PER_CTR0 +

		       (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx);

	} else {

		return box->pmu->type->perf_ctr +

		       (box->pmu->type->pair_ctr_ctl ? 2 * idx : idx) +

		       uncore_msr_box_offset(box);

	}

}



static inline

unsigned uncore_fixed_ctl(struct intel_uncore_box *box)

arch/x86/events/intel/uncore_snb.c

+5 −1
Original line number Diff line number Diff line
@@ -221,6 +221,10 @@ static void skl_uncore_msr_init_box(struct intel_uncore_box *box) 
		wrmsrl(SKL_UNC_PERF_GLOBAL_CTL,

			SNB_UNC_GLOBAL_CTL_EN | SKL_UNC_GLOBAL_CTL_CORE_ALL);

	}



	/* The 8th CBOX has different MSR space */

	if (box->pmu->pmu_idx == 7)

		__set_bit(UNCORE_BOX_FLAG_CFL8_CBOX_MSR_OFFS, &box->flags);

}



static void skl_uncore_msr_enable_box(struct intel_uncore_box *box)
@@ -247,7 +251,7 @@ static struct intel_uncore_ops skl_uncore_msr_ops = { 
static struct intel_uncore_type skl_uncore_cbox = {

	.name		= "cbox",

	.num_counters   = 4,

	.num_boxes	= 5,

	.num_boxes	= 8,

	.perf_ctr_bits	= 44,

	.fixed_ctr_bits	= 48,

	.perf_ctr	= SNB_UNC_CBO_0_PER_CTR0,