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Commit 4d24c9b0 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "ARM: dts: msm: add 2nd UFS for Quin SA8195 LXC VM"

parents 2c7413bd 370b9a55

qcom/sa8195-vm-lv-cnss-lxc.dtsi

0 → 100644
+577 −0
Original line number Diff line number Diff line 
&cnss_pins {

	cnss_wlan_en_active2: cnss_wlan_en_active2 {

		mux {

			pins = "gpio170";

			function = "gpio";

		};



		config {

			pins = "gpio170";

			drive-strength = <16>;

			output-high;

			bias-pull-up;

		};

	};



	cnss_wlan_en_sleep2: cnss_wlan_en_sleep2 {

		mux {

			pins = "gpio170";

			function = "gpio";

		};



		config {

			pins = "gpio170";

			drive-strength = <2>;

			output-low;

			bias-pull-down;

		};

	};

};



&cnss_pcie {

	status = "disabled";

};



&soc {

	/* Support Dual Hastings case*/

	cnss_pcie0: qcom,cnss-qca-converged0 {

		compatible = "qcom,cnss-qca-converged";



		qcom,converged-dt;

		qcom,wlan-rc-num = <0>;

		qcom,bus-type=<0>;

		qcom,qrtr_node_id = <0x10>;

		qcom,notify-modem-status;



		#address-cells=<1>;

		#size-cells=<1>;

		ranges = <0xb0000000 0xb0000000 0x10000>;



		vdd-wlan-ctrl1-supply = <&vreg_conn_pa>;

		vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>;

		vdd-wlan-supply = <&vreg_wlan>;

		vdd-wlan-aon-supply = <&pm8195_1_s5>;

		vdd-wlan-rfa1-supply = <&pm8195_1_s2>;

		vdd-wlan-rfa2-supply = <&pm8195_2_s5>;

		vdd-wlan-rfa3-supply = <&pm8195_2_l7>;



		wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2";

		qcom,vdd-wlan-ctrl1-config = <0 0 0 0>;

		qcom,vdd-wlan-ctrl2-config = <0 0 0 0>;

		wlan-en-gpio = <&tlmm 169 0>;

		pinctrl-names = "wlan_en_active", "wlan_en_sleep";

		pinctrl-0 = <&cnss_wlan_en_active>;

		pinctrl-1 = <&cnss_wlan_en_sleep>;



		chip_cfg@0 {

			reg = <0xb0000000 0x10000>;



			reg-names = "smmu_iova_ipa";



			supported-ids = <0x003e>;

			wlan_vregs = "vdd-wlan";

			qcom,vdd-wlan-info = <0 0 0 10>;



			qcom,wlan-ramdump-dynamic = <0x200000>;

		};



		chip_cfg@1 {

			reg = <0xb0000000 0x10000>;

			reg-names = "smmu_iova_ipa";



			supported-ids = <0x1101>;

			wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1",

				   "vdd-wlan-rfa2", "vdd-wlan-rfa3";

			qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>;

			qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>;

			qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>;

			qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>;



			qcom,wlan-ramdump-dynamic = <0x400000>;

			mhi,max-channels = <30>;

			mhi,timeout = <10000>;

			mhi,buffer-len = <0x8000>;

			mhi,m2-no-db-access;



			mhi_channels {

				#address-cells = <1>;

				#size-cells = <0>;

				mhi_chan@0 {

					reg = <0>;

					label = "LOOPBACK";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@1 {

					reg = <1>;

					label = "LOOPBACK";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@4 {

					reg = <4>;

					label = "DIAG";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@5 {

					reg = <5>;

					label = "DIAG";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@20 {

					reg = <20>;

					label = "IPCR";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <1>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

					mhi,auto-start;

				};



				mhi_chan@21 {

					reg = <21>;

					label = "IPCR";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

					mhi,auto-queue;

					mhi,auto-start;

				};

			};



			mhi_events {

				mhi_event@0 {

					mhi,num-elements = <32>;

					mhi,intmod = <1>;

					mhi,msi = <1>;

					mhi,priority = <1>;

					mhi,brstmode = <2>;

					mhi,data-type = <1>;

				};



				mhi_event@1 {

					mhi,num-elements = <256>;

					mhi,intmod = <1>;

					mhi,msi = <2>;

					mhi,priority = <1>;

					mhi,brstmode = <2>;

				};

			};

		};



		chip_cfg@2 {

			reg = <0xb0000000 0x10000>;

			reg-names = "smmu_iova_ipa";



			supported-ids = <0x1102>;

			wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1",

				   "vdd-wlan-rfa2", "vdd-wlan-rfa3";

			qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>;

			qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>;

			qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>;

			qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>;



			qcom,wlan-ramdump-dynamic = <0x300000>;

			mhi,max-channels = <30>;

			mhi,timeout = <10000>;

			mhi,ee = <0x3>, <0x4>;

			mhi,ee-names = "SBL", "RDDM";

			mhi,bhie-offset = <0x0324>;



			mhi_channels {

				#address-cells = <1>;

				#size-cells = <0>;

				mhi_chan@0 {

					reg = <0>;

					label = "LOOPBACK";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@1 {

					reg = <1>;

					label = "LOOPBACK";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@4 {

					reg = <4>;

					label = "DIAG";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@5 {

					reg = <5>;

					label = "DIAG";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@16 {

					reg = <16>;

					label = "IPCR";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <1>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

					mhi,auto-start;

				};



				mhi_chan@17 {

					reg = <17>;

					label = "IPCR";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

					mhi,auto-queue;

					mhi,auto-start;

				};

			};



			mhi_events {

				mhi_event@0 {

					mhi,num-elements = <32>;

					mhi,intmod = <1>;

					mhi,msi = <1>;

					mhi,priority = <1>;

					mhi,brstmode = <2>;

					mhi,data-type = <1>;

				};



				mhi_event@1 {

					mhi,num-elements = <256>;

					mhi,intmod = <1>;

					mhi,msi = <2>;

					mhi,priority = <1>;

					mhi,brstmode = <2>;

				};

			};

		};

	};



	cnss_pcie2: qcom,cnss-qca-converged2 {

		compatible = "qcom,cnss-qca-converged";



		qcom,converged-dt;

		qcom,wlan-rc-num = <2>;

		qcom,bus-type=<0>;

		qcom,qrtr_node_id = <0x20>;

		qcom,notify-modem-status;



		#address-cells=<1>;

		#size-cells=<1>;

		ranges = <0xd0000000 0xd0000000 0x10000>;



		vdd-wlan-ctrl1-supply = <&vreg_conn_pa>;

		vdd-wlan-ctrl2-supply = <&vreg_conn_1p8>;

		vdd-wlan-supply = <&vreg_wlan>;

		vdd-wlan-aon-supply = <&pm8195_1_s5>;

		vdd-wlan-rfa1-supply = <&pm8195_1_s2>;

		vdd-wlan-rfa2-supply = <&pm8195_2_s5>;

		vdd-wlan-rfa3-supply = <&pm8195_2_l7>;



		wlan_vregs = "vdd-wlan-ctrl1", "vdd-wlan-ctrl2";

		qcom,vdd-wlan-ctrl1-config = <0 0 0 0>;

		qcom,vdd-wlan-ctrl2-config = <0 0 0 0>;

		wlan-en-gpio = <&tlmm 170 0>;

		pinctrl-names = "wlan_en_active", "wlan_en_sleep";

		pinctrl-0 = <&cnss_wlan_en_active2>;

		pinctrl-1 = <&cnss_wlan_en_sleep2>;



		chip_cfg@0 {

			reg = <0xd0000000 0x10000>;

			reg-names = "smmu_iova_ipa";



			supported-ids = <0x003e>;

			wlan_vregs = "vdd-wlan";

			qcom,vdd-wlan-info = <0 0 0 10>;



			qcom,wlan-ramdump-dynamic = <0x200000>;

		};



		chip_cfg@1 {

			reg = <0xd0000000 0x10000>;

			reg-names = "smmu_iova_ipa";



			supported-ids = <0x1101>;

			wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1",

				   "vdd-wlan-rfa2", "vdd-wlan-rfa3";

			qcom,vdd-wlan-aon-config = <1000000 1000000 0 0 1>;

			qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>;

			qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>;

			qcom,vdd-wlan-rfa3-config = <1900000 1900000 450000 0 1>;



			qcom,wlan-ramdump-dynamic = <0x400000>;

			mhi,max-channels = <30>;

			mhi,timeout = <10000>;

			mhi,buffer-len = <0x8000>;

			mhi,m2-no-db-access;



			mhi_channels {

				#address-cells = <1>;

				#size-cells = <0>;

				mhi_chan@0 {

					reg = <0>;

					label = "LOOPBACK";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@1 {

					reg = <1>;

					label = "LOOPBACK";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@20 {

					reg = <20>;

					label = "IPCR";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <1>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

					mhi,auto-start;

				};



				mhi_chan@21 {

					reg = <21>;

					label = "IPCR";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

					mhi,auto-queue;

					mhi,auto-start;

				};

			};



			mhi_events {

				mhi_event@0 {

					mhi,num-elements = <32>;

					mhi,intmod = <1>;

					mhi,msi = <1>;

					mhi,priority = <1>;

					mhi,brstmode = <2>;

					mhi,data-type = <1>;

				};



				mhi_event@1 {

					mhi,num-elements = <256>;

					mhi,intmod = <1>;

					mhi,msi = <2>;

					mhi,priority = <1>;

					mhi,brstmode = <2>;

				};

			};

		};



		chip_cfg@2 {

			reg = <0xd0000000 0x10000>;

			reg-names = "smmu_iova_ipa";



			supported-ids = <0x1102>;

			wlan_vregs = "vdd-wlan-aon", "vdd-wlan-rfa1",

				   "vdd-wlan-rfa2", "vdd-wlan-rfa3";

			qcom,vdd-wlan-aon-config = <1055000 1055000 0 0 1>;

			qcom,vdd-wlan-rfa1-config = <1370000 1370000 0 0 1>;

			qcom,vdd-wlan-rfa2-config = <2040000 2040000 0 0 1>;

			qcom,vdd-wlan-rfa3-config = <1900000 1900000 0 0 1>;



			qcom,wlan-ramdump-dynamic = <0x300000>;

			mhi,max-channels = <30>;

			mhi,timeout = <10000>;

			mhi,ee = <0x3>, <0x4>;

			mhi,ee-names = "SBL", "RDDM";

			mhi,bhie-offset = <0x0324>;



			mhi_channels {

				#address-cells = <1>;

				#size-cells = <0>;

				mhi_chan@0 {

					reg = <0>;

					label = "LOOPBACK";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@1 {

					reg = <1>;

					label = "LOOPBACK";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@4 {

					reg = <4>;

					label = "DIAG";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@5 {

					reg = <5>;

					label = "DIAG";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

				};



				mhi_chan@16 {

					reg = <16>;

					label = "IPCR";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <1>;

					mhi,data-type = <1>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

					mhi,auto-start;

				};



				mhi_chan@17 {

					reg = <17>;

					label = "IPCR";

					mhi,num-elements = <32>;

					mhi,event-ring = <1>;

					mhi,chan-dir = <2>;

					mhi,data-type = <0>;

					mhi,doorbell-mode = <2>;

					mhi,ee = <0x14>;

					mhi,auto-queue;

					mhi,auto-start;

				};

			};



			mhi_events {

				mhi_event@0 {

					mhi,num-elements = <32>;

					mhi,intmod = <1>;

					mhi,msi = <1>;

					mhi,priority = <1>;

					mhi,brstmode = <2>;

					mhi,data-type = <1>;

				};



				mhi_event@1 {

					mhi,num-elements = <256>;

					mhi,intmod = <1>;

					mhi,msi = <2>;

					mhi,priority = <1>;

					mhi,brstmode = <2>;

				};

			};

		};

	};

};



&pcie_rc0 {

	cnss_pci: cnss_pci {

		reg = <0 0 0 0 0>;

		qcom,iommu-group = <&cnss_pci_iommu_group>;



		#address-cells = <1>;

		#size-cells = <1>;



		cnss_pci_iommu_group: cnss_pci_iommu_group {

			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;

			qcom,iommu-dma = "bypass";

			qcom,iommu-faults = "stall-disable", "no-CFRE",

						"non-fatal";

		};

	};

};



&pcie_rc2 {

	cnss_pci2: cnss_pci2 {

		reg = <0 0 0 0 0>;

		qcom,iommu-group = <&cnss_pci_iommu_group2>;



		#address-cells = <1>;

		#size-cells = <1>;



		cnss_pci_iommu_group2: cnss_pci_iommu_group2 {

			qcom,iommu-dma-addr-pool = <0xc0000000 0x10000000>;

			qcom,iommu-dma = "bypass";

			qcom,iommu-faults = "stall-disable", "no-CFRE",

						"non-fatal";

		};

	};

};

qcom/sa8195-vm-lv-lxc.dtsi

+15 −0
Original line number Diff line number Diff line
@@ -38,6 +38,10 @@ 
	status = "ok";

};



&linux_cma {

	size = <0x0 0x3c00000>;

};



&pcie0_msi {

	status = "ok";

};
@@ -53,3 +57,14 @@ 
&pcie2 {

	status = "ok";

};



#include "sa8195-vm-lv-cnss-lxc.dtsi"

#include "sa8195-vm-ufs.dtsi"



&ufs2phy_mem {

	status = "ok";

};



&ufshc2_mem {

	status = "ok";

};

qcom/sa8195-vm-ufs.dtsi

0 → 100644
+211 −0
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,rpmh.h>



&regulator {

	L17A: pm8195_1_l17: regulator-pm8195-1-l17 {

		regulator-name = "ldoa17";

		regulator-min-microvolt = <1700000>;

		regulator-max-microvolt = <3544000>;

		regulator-always-on;

		regulator-allow-set-load;

	};



	L5C: pm8195_2_l5: regulator-pm8195-2-l5 {

		regulator-name = "ldoc5";

		regulator-min-microvolt = <1200000>;

		regulator-max-microvolt = <1200000>;

	};



	L10E: pm8195_3_l10: regulator-pm8195-3-l10 {

		regulator-name = "ldoe10";

		regulator-min-microvolt = <2500000>;

		regulator-max-microvolt = <3544000>;

		regulator-always-on;

	};



	S4A: pm8195_1_s4: regulator-pm8195-1-s4 {

		regulator-name = "smpa4";

		regulator-min-microvolt = <1800000>;

		regulator-max-microvolt = <1800000>;

	};

};



&soc {

	ufs2_ice: ufs2ice@1d70000 {

		compatible = "qcom,ice";

		reg = <0x1d70000 0x8000>;

		qcom,enable-ice-clk;

		clock-names = "ufs_core_clk",

				"iface_clk", "ice_core_clk";

		clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>,

			 <&gcc GCC_UFS_CARD_2_AHB_CLK>,

			 <&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>;

		qcom,op-freq-hz = <0>, <0>, <300000000>;

		vdd-hba-supply = <&ufs_card_2_gdsc>;

		qcom,msm-bus,name = "ufs_ice_noc";

		qcom,msm-bus,num-cases = <2>;

		qcom,msm-bus,num-paths = <1>;

		qcom,msm-bus,vectors-KBps =

				<1 650 0 0>,    /* No vote */

				<1 650 1000 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",

					"MAX";

		qcom,instance-type = "ufs";



		status = "disabled";

	};



	ufs2phy_mem: ufsphy2_mem@1d67000 {

		compatible = "qcom,ufs-phy-qmp-v4";

		reg = <0x1d67000 0xe00>; /* PHY regs */

		reg-names = "phy_mem";

		#phy-cells = <0>;

		ufs-qcom-crypto = <&ufs2_ice>;



		lanes-per-direction = <2>;



		vdda-phy-supply = <&pm8195_3_l5>;

		vdda-pll-supply = <&pm8195_1_l9>;

		vdda-phy-max-microamp = <138000>;

		vdda-pll-max-microamp = <65100>;



		clock-names = "ref_clk_src",

			"ref_aux_clk";

		clocks = <&dummycc RPMH_CXO_CLK>,

			<&gcc GCC_UFS_CARD_2_PHY_AUX_CLK>;



		status = "disabled";

	};



	ufshc2_mem: ufshc2@1d64000 {

		compatible = "qcom,ufshc";

		reg = <0x1d64000 0x3000>;

		interrupts = <GIC_SPI 649 IRQ_TYPE_LEVEL_HIGH>;

		phys = <&ufs2phy_mem>;

		phy-names = "ufsphy";

		ufs-qcom-crypto = <&ufs2_ice>;

		spm-level = <5>;

		rpm-level = <1>;



		lanes-per-direction = <2>;

		dev-ref-clk-freq = <0>; /* 19.2 MHz */



		vdd-hba-supply = <&ufs_card_2_gdsc>;

		vdd-hba-fixed-regulator;

		vcc-supply = <&pm8195_1_l17>;

		vcc-voltage-level = <2894000 2904000>;

		vcc-low-voltage-sup;

		vccq-supply = <&pm8195_2_l5>;

		vccq2-supply = <&pm8195_1_s4>;

		vcc-max-microamp = <750000>;

		vccq-max-microamp = <750000>;

		vccq2-max-microamp = <750000>;



		qcom,vddp-ref-clk-supply = <&pm8195_2_l5>;

		qcom,vddp-ref-clk-max-microamp = <100>;

		qcom,vccq-parent-supply = <&pm8195_1_s2>;

		qcom,vccq-parent-max-microamp = <210000>;



		qcom,disable-lpm;



		clock-names =

			"core_clk",

			"bus_aggr_clk",

			"iface_clk",

			"core_clk_unipro",

			"core_clk_ice",

			"ref_clk",

			"tx_lane0_sync_clk",

			"rx_lane0_sync_clk",

			"rx_lane1_sync_clk";

		clocks =

			<&gcc GCC_UFS_CARD_2_AXI_CLK>,

			<&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>,

			<&gcc GCC_UFS_CARD_2_AHB_CLK>,

			<&gcc GCC_UFS_CARD_2_UNIPRO_CORE_CLK>,

			<&gcc GCC_UFS_CARD_2_ICE_CORE_CLK>,

			<&dummycc RPMH_CXO_CLK>,

			<&gcc GCC_UFS_CARD_2_TX_SYMBOL_0_CLK>,

			<&gcc GCC_UFS_CARD_2_RX_SYMBOL_0_CLK>,

			<&gcc GCC_UFS_CARD_2_RX_SYMBOL_1_CLK>;

		freq-table-hz =

			<37500000 300000000>,

			<0 0>,

			<0 0>,

			<37500000 300000000>,

			<37500000 300000000>,

			<0 0>,

			<0 0>,

			<0 0>,

			<0 0>;



		qcom,msm-bus,name = "ufshc_mem";

		qcom,msm-bus,num-cases = <26>;

		qcom,msm-bus,num-paths = <2>;

		qcom,msm-bus,vectors-KBps =

		/*

		 * During HS G3 UFS runs at nominal voltage corner, vote

		 * higher bandwidth to push other buses in the data path

		 * to run at nominal to achieve max throughput.

		 * 4GBps pushes BIMC to run at nominal.

		 * 200MBps pushes CNOC to run at nominal.

		 * Vote for half of this bandwidth for HS G3 1-lane.

		 * For max bandwidth, vote high enough to push the buses

		 * to run in turbo voltage corner.

		 */

		<163 512 0 0>, <1 798 0 0>,          /* No vote */

		<163 512 922 0>, <1 798 1000 0>,     /* PWM G1 */

		<163 512 1844 0>, <1 798 1000 0>,    /* PWM G2 */

		<163 512 3688 0>, <1 798 1000 0>,    /* PWM G3 */

		<163 512 7376 0>, <1 798 1000 0>,    /* PWM G4 */

		<163 512 1844 0>, <1 798 1000 0>,    /* PWM G1 L2 */

		<163 512 3688 0>, <1 798 1000 0>,    /* PWM G2 L2 */

		<163 512 7376 0>, <1 798 1000 0>,    /* PWM G3 L2 */

		<163 512 14752 0>, <1 798 1000 0>,   /* PWM G4 L2 */

		<163 512 127796 0>, <1 798 1000 0>,  /* HS G1 RA */

		<163 512 255591 0>, <1 798 1000 0>,  /* HS G2 RA */

		<163 512 2097152 0>, <1 798 102400 0>,  /* HS G3 RA */

		<163 512 4194304 0>, <1 798 204800 0>,  /* HS G4 RA */

		<163 512 255591 0>, <1 798 1000 0>,  /* HS G1 RA L2 */

		<163 512 511181 0>, <1 798 1000 0>,  /* HS G2 RA L2 */

		<163 512 4194304 0>, <1 798 204800 0>, /* HS G3 RA L2 */

		<163 512 8388608 0>, <1 798 409600 0>, /* HS G4 RA L2 */

		<163 512 149422 0>, <1 798 1000 0>,  /* HS G1 RB */

		<163 512 298189 0>, <1 798 1000 0>,  /* HS G2 RB */

		<163 512 2097152 0>, <1 798 102400 0>,  /* HS G3 RB */

		<163 512 4194304 0>, <1 798 204800 0>,  /* HS G4 RB */

		<163 512 298189 0>, <1 798 1000 0>,  /* HS G1 RB L2 */

		<163 512 596378 0>, <1 798 1000 0>,  /* HS G2 RB L2 */

		/* As UFS working in HS G3 RB L2 mode, aggregated

		 * bandwidth (AB) should take care of providing

		 * optimum throughput requested. However, as tested,

		 * in order to scale up CNOC clock, instantaneous

		 * bindwidth (IB) needs to be given a proper value too.

		 */

		<163 512 4194304 0>, <1 798 204800 409600>, /* HS G3 RB L2 */

		<163 512 8388608 0>, <1 798 409600 409600>, /* HS G4 RB L2 */

		<163 512 7643136 0>, <1 798 307200 0>; /* Max. bandwidth */



		qcom,bus-vector-names = "MIN",

		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",

		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",

		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",

		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",

		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",

		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",

		"MAX";



		/* PM QoS */

		qcom,pm-qos-cpu-groups = <0x0f 0xf0>;

		qcom,pm-qos-cpu-group-latency-us = <44 44>;

		qcom,pm-qos-default-cpu = <0>;



		pinctrl-names = "dev-reset-assert", "dev-reset-deassert";

		pinctrl-0 = <&ufs0_dev_reset_assert>;

		pinctrl-1 = <&ufs0_dev_reset_deassert>;



		resets = <&gcc GCC_UFS_CARD_2_BCR>;

		reset-names = "core_reset";



		status = "disabled";

	};

};

qcom/sa8195-vm.dtsi

+5 −1
Original line number Diff line number Diff line
@@ -145,7 +145,7 @@ 
		gpio = <&tlmm 174 0>;

	};



	qcom,cnss-qca-converged {

	cnss_pcie: qcom,cnss-qca-converged {

		compatible = "qcom,cnss-qca-converged";



		qcom,converged-dt;
@@ -778,6 +778,10 @@ 
		regulator-name = "pcie_3_gdsc";

	};



	ufs_card_2_gdsc: ufs_card_2_gdsc {

		regulator-name = "ufs_card_2_gdsc";

	};



	L2A: pm8195_1_l2: regulator-pm8195-1-l2 {

		regulator-name = "ldoa2";

		regulator-min-microvolt = <1800000>;

qcom/sdmshrike-pinctrl.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -3573,7 +3573,7 @@ 
			};

		};



		cnss_pins {

		cnss_pins: cnss_pins {

			cnss_wlan_en_active: cnss_wlan_en_active {

				mux {

					pins = "gpio169";