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Commit 4c93b2bd authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "serial: msm_geni_serial: Manage HSUART clocks when read HW Ver"

parents d184fa35 c1d740e8

drivers/tty/serial/msm_geni_serial.c

+12 −17
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0-only

/*

 * Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.

 */



#include <linux/bitmap.h>
@@ -170,6 +170,7 @@ struct msm_geni_serial_port { 
	struct msm_geni_serial_ver_info ver_info;

	u32 cur_tx_remaining;

	bool startup_in_progress;

	bool is_console;

};



static const struct uart_ops msm_geni_serial_pops;
@@ -1992,10 +1993,6 @@ static void msm_geni_serial_set_termios(struct uart_port *uport, 
	unsigned long clk_rate;

	unsigned long flags;



	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	if (!uart_console(uport)) {

		int ret = msm_geni_serial_power_on(uport);
@@ -2334,10 +2331,6 @@ msm_geni_serial_earlycon_setup(struct earlycon_device *dev, 
	 */

	msm_geni_serial_poll_cancel_tx(uport);



	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	se_get_packing_config(8, 1, false, &cfg0, &cfg1);

	geni_se_init(uport->membase, (DEF_FIFO_DEPTH_WORDS >> 1),

					(DEF_FIFO_DEPTH_WORDS - 2));
@@ -2530,6 +2523,8 @@ static int msm_geni_serial_get_ver_info(struct uart_port *uport) 
	int hw_ver, ret = 0;

	struct msm_geni_serial_port *msm_port = GET_DEV_PORT(uport);



	/* clks_on/off only for HSUART, as console remains actve */

	if (!msm_port->is_console)

		se_geni_clks_on(&msm_port->serial_rsc);

	/* Basic HW and FW info */

	if (unlikely(get_se_proto(uport->membase) != UART)) {
@@ -2558,6 +2553,7 @@ static int msm_geni_serial_get_ver_info(struct uart_port *uport) 
			msm_port->ver_info.hw_minor_ver,

			msm_port->ver_info.hw_step_ver);

exit_ver_info:

	if (!msm_port->is_console)

		se_geni_clks_off(&msm_port->serial_rsc);

	return ret;

}
@@ -2649,6 +2645,7 @@ static int msm_geni_serial_probe(struct platform_device *pdev) 
		goto exit_geni_serial_probe;



	dev_port->serial_rsc.ctrl_dev = &pdev->dev;

	dev_port->is_console = is_console;



	if (of_property_read_u32(pdev->dev.of_node, "qcom,wakeup-byte",

					&wake_char)) {
@@ -2782,10 +2779,6 @@ static int msm_geni_serial_probe(struct platform_device *pdev) 
		pm_runtime_enable(&pdev->dev);

	}



	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_M_CLK_CFG);

	geni_write_reg_nolog(0x21, uport->membase, GENI_SER_S_CLK_CFG);

	geni_read_reg_nolog(uport->membase, GENI_SER_M_CLK_CFG);



	dev_info(&pdev->dev, "Serial port%d added.FifoSize %d is_console%d\n",

				line, uport->fifosize, is_console);

	device_create_file(uport->dev, &dev_attr_loopback);
@@ -2793,11 +2786,13 @@ static int msm_geni_serial_probe(struct platform_device *pdev) 
	device_create_file(uport->dev, &dev_attr_ver_info);

	msm_geni_serial_debug_init(uport, is_console);

	dev_port->port_setup = false;



	ret = msm_geni_serial_get_ver_info(uport);

	if (ret)

	if (ret) {

		dev_err(&pdev->dev, "Failed to Read FW ver: %d\n", ret);

		goto exit_geni_serial_probe;

	}

	return uart_add_one_port(drv, uport);



exit_geni_serial_probe:

	return ret;

}