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Commit 4c805654 authored by Alexandre Belloni's avatar Alexandre Belloni Committed by Nicolas Ferre
Browse files

ARM: at91: remove SoC headers 



Remove the now useless SoC headers.

Signed-off-by: default avatarAlexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent f56d8f7c

arch/arm/mach-at91/include/mach/at91rm9200.h

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Original line number Diff line number Diff line 
/*

 * arch/arm/mach-at91/include/mach/at91rm9200.h

 *

 * Copyright (C) 2005 Ivan Kokshaysky

 * Copyright (C) SAN People

 *

 * Common definitions.

 * Based on AT91RM9200 datasheet revision E.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91RM9200_H

#define AT91RM9200_H



/*

 * Peripheral identifiers/interrupts.

 */

#define AT91RM9200_ID_PIOA	2	/* Parallel IO Controller A */

#define AT91RM9200_ID_PIOB	3	/* Parallel IO Controller B */

#define AT91RM9200_ID_PIOC	4	/* Parallel IO Controller C */

#define AT91RM9200_ID_PIOD	5	/* Parallel IO Controller D */

#define AT91RM9200_ID_US0	6	/* USART 0 */

#define AT91RM9200_ID_US1	7	/* USART 1 */

#define AT91RM9200_ID_US2	8	/* USART 2 */

#define AT91RM9200_ID_US3	9	/* USART 3 */

#define AT91RM9200_ID_MCI	10	/* Multimedia Card Interface */

#define AT91RM9200_ID_UDP	11	/* USB Device Port */

#define AT91RM9200_ID_TWI	12	/* Two-Wire Interface */

#define AT91RM9200_ID_SPI	13	/* Serial Peripheral Interface */

#define AT91RM9200_ID_SSC0	14	/* Serial Synchronous Controller 0 */

#define AT91RM9200_ID_SSC1	15	/* Serial Synchronous Controller 1 */

#define AT91RM9200_ID_SSC2	16	/* Serial Synchronous Controller 2 */

#define AT91RM9200_ID_TC0	17	/* Timer Counter 0 */

#define AT91RM9200_ID_TC1	18	/* Timer Counter 1 */

#define AT91RM9200_ID_TC2	19	/* Timer Counter 2 */

#define AT91RM9200_ID_TC3	20	/* Timer Counter 3 */

#define AT91RM9200_ID_TC4	21	/* Timer Counter 4 */

#define AT91RM9200_ID_TC5	22	/* Timer Counter 5 */

#define AT91RM9200_ID_UHP	23	/* USB Host port */

#define AT91RM9200_ID_EMAC	24	/* Ethernet MAC */

#define AT91RM9200_ID_IRQ0	25	/* Advanced Interrupt Controller (IRQ0) */

#define AT91RM9200_ID_IRQ1	26	/* Advanced Interrupt Controller (IRQ1) */

#define AT91RM9200_ID_IRQ2	27	/* Advanced Interrupt Controller (IRQ2) */

#define AT91RM9200_ID_IRQ3	28	/* Advanced Interrupt Controller (IRQ3) */

#define AT91RM9200_ID_IRQ4	29	/* Advanced Interrupt Controller (IRQ4) */

#define AT91RM9200_ID_IRQ5	30	/* Advanced Interrupt Controller (IRQ5) */

#define AT91RM9200_ID_IRQ6	31	/* Advanced Interrupt Controller (IRQ6) */





/*

 * Peripheral physical base addresses.

 */

#define AT91RM9200_BASE_TCB0	0xfffa0000

#define AT91RM9200_BASE_TC0	0xfffa0000

#define AT91RM9200_BASE_TC1	0xfffa0040

#define AT91RM9200_BASE_TC2	0xfffa0080

#define AT91RM9200_BASE_TCB1	0xfffa4000

#define AT91RM9200_BASE_TC3	0xfffa4000

#define AT91RM9200_BASE_TC4	0xfffa4040

#define AT91RM9200_BASE_TC5	0xfffa4080

#define AT91RM9200_BASE_UDP	0xfffb0000

#define AT91RM9200_BASE_MCI	0xfffb4000

#define AT91RM9200_BASE_TWI	0xfffb8000

#define AT91RM9200_BASE_EMAC	0xfffbc000

#define AT91RM9200_BASE_US0	0xfffc0000

#define AT91RM9200_BASE_US1	0xfffc4000

#define AT91RM9200_BASE_US2	0xfffc8000

#define AT91RM9200_BASE_US3	0xfffcc000

#define AT91RM9200_BASE_SSC0	0xfffd0000

#define AT91RM9200_BASE_SSC1	0xfffd4000

#define AT91RM9200_BASE_SSC2	0xfffd8000

#define AT91RM9200_BASE_SPI	0xfffe0000





/*

 * System Peripherals

 */

#define AT91RM9200_BASE_DBGU	AT91_BASE_DBGU0	/* Debug Unit */

#define AT91RM9200_BASE_PIOA	0xfffff400	/* PIO Controller A */

#define AT91RM9200_BASE_PIOB	0xfffff600	/* PIO Controller B */

#define AT91RM9200_BASE_PIOC	0xfffff800	/* PIO Controller C */

#define AT91RM9200_BASE_PIOD	0xfffffa00	/* PIO Controller D */

#define AT91RM9200_BASE_ST	0xfffffd00	/* System Timer */

#define AT91RM9200_BASE_RTC	0xfffffe00	/* Real-Time Clock */

#define AT91RM9200_BASE_MC	0xffffff00	/* Memory Controllers */



/*

 * Internal Memory.

 */

#define AT91RM9200_ROM_BASE	0x00100000	/* Internal ROM base address */

#define AT91RM9200_ROM_SIZE	SZ_128K		/* Internal ROM size (128Kb) */



#define AT91RM9200_SRAM_BASE	0x00200000	/* Internal SRAM base address */

#define AT91RM9200_SRAM_SIZE	SZ_16K		/* Internal SRAM size (16Kb) */



#define AT91RM9200_UHP_BASE	0x00300000	/* USB Host controller */





#endif

arch/arm/mach-at91/include/mach/at91sam9260.h

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/*

 * arch/arm/mach-at91/include/mach/at91sam9260.h

 *

 * (C) 2006 Andrew Victor

 *

 * Common definitions.

 * Based on AT91SAM9260 datasheet revision A (Preliminary).

 *

 * Includes also definitions for AT91SAM9XE and AT91SAM9G families

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91SAM9260_H

#define AT91SAM9260_H



/*

 * Peripheral identifiers/interrupts.

 */

#define AT91SAM9260_ID_PIOA	2	/* Parallel IO Controller A */

#define AT91SAM9260_ID_PIOB	3	/* Parallel IO Controller B */

#define AT91SAM9260_ID_PIOC	4	/* Parallel IO Controller C */

#define AT91SAM9260_ID_ADC	5	/* Analog-to-Digital Converter */

#define AT91SAM9260_ID_US0	6	/* USART 0 */

#define AT91SAM9260_ID_US1	7	/* USART 1 */

#define AT91SAM9260_ID_US2	8	/* USART 2 */

#define AT91SAM9260_ID_MCI	9	/* Multimedia Card Interface */

#define AT91SAM9260_ID_UDP	10	/* USB Device Port */

#define AT91SAM9260_ID_TWI	11	/* Two-Wire Interface */

#define AT91SAM9260_ID_SPI0	12	/* Serial Peripheral Interface 0 */

#define AT91SAM9260_ID_SPI1	13	/* Serial Peripheral Interface 1 */

#define AT91SAM9260_ID_SSC	14	/* Serial Synchronous Controller */

#define AT91SAM9260_ID_TC0	17	/* Timer Counter 0 */

#define AT91SAM9260_ID_TC1	18	/* Timer Counter 1 */

#define AT91SAM9260_ID_TC2	19	/* Timer Counter 2 */

#define AT91SAM9260_ID_UHP	20	/* USB Host port */

#define AT91SAM9260_ID_EMAC	21	/* Ethernet */

#define AT91SAM9260_ID_ISI	22	/* Image Sensor Interface */

#define AT91SAM9260_ID_US3	23	/* USART 3 */

#define AT91SAM9260_ID_US4	24	/* USART 4 */

#define AT91SAM9260_ID_US5	25	/* USART 5 */

#define AT91SAM9260_ID_TC3	26	/* Timer Counter 3 */

#define AT91SAM9260_ID_TC4	27	/* Timer Counter 4 */

#define AT91SAM9260_ID_TC5	28	/* Timer Counter 5 */

#define AT91SAM9260_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */

#define AT91SAM9260_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */

#define AT91SAM9260_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */





/*

 * User Peripheral physical base addresses.

 */

#define AT91SAM9260_BASE_TCB0		0xfffa0000

#define AT91SAM9260_BASE_TC0		0xfffa0000

#define AT91SAM9260_BASE_TC1		0xfffa0040

#define AT91SAM9260_BASE_TC2		0xfffa0080

#define AT91SAM9260_BASE_UDP		0xfffa4000

#define AT91SAM9260_BASE_MCI		0xfffa8000

#define AT91SAM9260_BASE_TWI		0xfffac000

#define AT91SAM9260_BASE_US0		0xfffb0000

#define AT91SAM9260_BASE_US1		0xfffb4000

#define AT91SAM9260_BASE_US2		0xfffb8000

#define AT91SAM9260_BASE_SSC		0xfffbc000

#define AT91SAM9260_BASE_ISI		0xfffc0000

#define AT91SAM9260_BASE_EMAC		0xfffc4000

#define AT91SAM9260_BASE_SPI0		0xfffc8000

#define AT91SAM9260_BASE_SPI1		0xfffcc000

#define AT91SAM9260_BASE_US3		0xfffd0000

#define AT91SAM9260_BASE_US4		0xfffd4000

#define AT91SAM9260_BASE_US5		0xfffd8000

#define AT91SAM9260_BASE_TCB1		0xfffdc000

#define AT91SAM9260_BASE_TC3		0xfffdc000

#define AT91SAM9260_BASE_TC4		0xfffdc040

#define AT91SAM9260_BASE_TC5		0xfffdc080

#define AT91SAM9260_BASE_ADC		0xfffe0000



/*

 * System Peripherals

 */

#define AT91SAM9260_BASE_ECC	0xffffe800

#define AT91SAM9260_BASE_SDRAMC	0xffffea00

#define AT91SAM9260_BASE_SMC	0xffffec00

#define AT91SAM9260_BASE_MATRIX	0xffffee00

#define AT91SAM9260_BASE_DBGU	AT91_BASE_DBGU0

#define AT91SAM9260_BASE_PIOA	0xfffff400

#define AT91SAM9260_BASE_PIOB	0xfffff600

#define AT91SAM9260_BASE_PIOC	0xfffff800

#define AT91SAM9260_BASE_RSTC	0xfffffd00

#define AT91SAM9260_BASE_SHDWC	0xfffffd10

#define AT91SAM9260_BASE_RTT	0xfffffd20

#define AT91SAM9260_BASE_PIT	0xfffffd30

#define AT91SAM9260_BASE_WDT	0xfffffd40

#define AT91SAM9260_BASE_GPBR	0xfffffd50





/*

 * Internal Memory.

 */

#define AT91SAM9260_ROM_BASE	0x00100000	/* Internal ROM base address */

#define AT91SAM9260_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */



#define AT91SAM9260_SRAM0_BASE	0x00200000	/* Internal SRAM 0 base address */

#define AT91SAM9260_SRAM0_SIZE	SZ_4K		/* Internal SRAM 0 size (4Kb) */

#define AT91SAM9260_SRAM1_BASE	0x00300000	/* Internal SRAM 1 base address */

#define AT91SAM9260_SRAM1_SIZE	SZ_4K		/* Internal SRAM 1 size (4Kb) */

#define AT91SAM9260_SRAM_BASE	0x002FF000	/* Internal SRAM base address */

#define AT91SAM9260_SRAM_SIZE	SZ_8K		/* Internal SRAM size (8Kb) */



#define AT91SAM9260_UHP_BASE	0x00500000	/* USB Host controller */



#define AT91SAM9XE_FLASH_BASE	0x00200000	/* Internal FLASH base address */

#define AT91SAM9XE_SRAM_BASE	0x00300000	/* Internal SRAM base address */



#define AT91SAM9G20_ROM_BASE	0x00100000	/* Internal ROM base address */

#define AT91SAM9G20_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */



#define AT91SAM9G20_SRAM0_BASE	0x00200000	/* Internal SRAM 0 base address */

#define AT91SAM9G20_SRAM0_SIZE	SZ_16K		/* Internal SRAM 0 size (16Kb) */

#define AT91SAM9G20_SRAM1_BASE	0x00300000	/* Internal SRAM 1 base address */

#define AT91SAM9G20_SRAM1_SIZE	SZ_16K		/* Internal SRAM 1 size (16Kb) */

#define AT91SAM9G20_SRAM_BASE	0x002FC000	/* Internal SRAM base address */

#define AT91SAM9G20_SRAM_SIZE	SZ_32K		/* Internal SRAM size (32Kb) */



#define AT91SAM9G20_UHP_BASE	0x00500000	/* USB Host controller */



#endif

arch/arm/mach-at91/include/mach/at91sam9261.h

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/*

 * arch/arm/mach-at91/include/mach/at91sam9261.h

 *

 * Copyright (C) SAN People

 *

 * Common definitions.

 * Based on AT91SAM9261 datasheet revision E. (Preliminary)

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91SAM9261_H

#define AT91SAM9261_H



/*

 * Peripheral identifiers/interrupts.

 */

#define AT91SAM9261_ID_PIOA	2	/* Parallel IO Controller A */

#define AT91SAM9261_ID_PIOB	3	/* Parallel IO Controller B */

#define AT91SAM9261_ID_PIOC	4	/* Parallel IO Controller C */

#define AT91SAM9261_ID_US0	6	/* USART 0 */

#define AT91SAM9261_ID_US1	7	/* USART 1 */

#define AT91SAM9261_ID_US2	8	/* USART 2 */

#define AT91SAM9261_ID_MCI	9	/* Multimedia Card Interface */

#define AT91SAM9261_ID_UDP	10	/* USB Device Port */

#define AT91SAM9261_ID_TWI	11	/* Two-Wire Interface */

#define AT91SAM9261_ID_SPI0	12	/* Serial Peripheral Interface 0 */

#define AT91SAM9261_ID_SPI1	13	/* Serial Peripheral Interface 1 */

#define AT91SAM9261_ID_SSC0	14	/* Serial Synchronous Controller 0 */

#define AT91SAM9261_ID_SSC1	15	/* Serial Synchronous Controller 1 */

#define AT91SAM9261_ID_SSC2	16	/* Serial Synchronous Controller 2 */

#define AT91SAM9261_ID_TC0	17	/* Timer Counter 0 */

#define AT91SAM9261_ID_TC1	18	/* Timer Counter 1 */

#define AT91SAM9261_ID_TC2	19	/* Timer Counter 2 */

#define AT91SAM9261_ID_UHP	20	/* USB Host port */

#define AT91SAM9261_ID_LCDC	21	/* LDC Controller */

#define AT91SAM9261_ID_IRQ0	29	/* Advanced Interrupt Controller (IRQ0) */

#define AT91SAM9261_ID_IRQ1	30	/* Advanced Interrupt Controller (IRQ1) */

#define AT91SAM9261_ID_IRQ2	31	/* Advanced Interrupt Controller (IRQ2) */





/*

 * User Peripheral physical base addresses.

 */

#define AT91SAM9261_BASE_TCB0		0xfffa0000

#define AT91SAM9261_BASE_TC0		0xfffa0000

#define AT91SAM9261_BASE_TC1		0xfffa0040

#define AT91SAM9261_BASE_TC2		0xfffa0080

#define AT91SAM9261_BASE_UDP		0xfffa4000

#define AT91SAM9261_BASE_MCI		0xfffa8000

#define AT91SAM9261_BASE_TWI		0xfffac000

#define AT91SAM9261_BASE_US0		0xfffb0000

#define AT91SAM9261_BASE_US1		0xfffb4000

#define AT91SAM9261_BASE_US2		0xfffb8000

#define AT91SAM9261_BASE_SSC0		0xfffbc000

#define AT91SAM9261_BASE_SSC1		0xfffc0000

#define AT91SAM9261_BASE_SSC2		0xfffc4000

#define AT91SAM9261_BASE_SPI0		0xfffc8000

#define AT91SAM9261_BASE_SPI1		0xfffcc000





/*

 * System Peripherals

 */

#define AT91SAM9261_BASE_SMC	0xffffec00

#define AT91SAM9261_BASE_MATRIX	0xffffee00

#define AT91SAM9261_BASE_SDRAMC	0xffffea00

#define AT91SAM9261_BASE_DBGU	AT91_BASE_DBGU0

#define AT91SAM9261_BASE_PIOA	0xfffff400

#define AT91SAM9261_BASE_PIOB	0xfffff600

#define AT91SAM9261_BASE_PIOC	0xfffff800

#define AT91SAM9261_BASE_RSTC	0xfffffd00

#define AT91SAM9261_BASE_SHDWC	0xfffffd10

#define AT91SAM9261_BASE_RTT	0xfffffd20

#define AT91SAM9261_BASE_PIT	0xfffffd30

#define AT91SAM9261_BASE_WDT	0xfffffd40

#define AT91SAM9261_BASE_GPBR	0xfffffd50





/*

 * Internal Memory.

 */

#define AT91SAM9261_SRAM_BASE	0x00300000	/* Internal SRAM base address */

#define AT91SAM9261_SRAM_SIZE	0x00028000	/* Internal SRAM size (160Kb) */



#define AT91SAM9G10_SRAM_BASE	AT91SAM9261_SRAM_BASE	/* Internal SRAM base address */

#define AT91SAM9G10_SRAM_SIZE	0x00004000	/* Internal SRAM size (16Kb) */



#define AT91SAM9261_ROM_BASE	0x00400000	/* Internal ROM base address */

#define AT91SAM9261_ROM_SIZE	SZ_32K		/* Internal ROM size (32Kb) */



#define AT91SAM9261_UHP_BASE	0x00500000	/* USB Host controller */

#define AT91SAM9261_LCDC_BASE	0x00600000	/* LDC controller */





#endif

arch/arm/mach-at91/include/mach/at91sam9263.h

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/*

 * arch/arm/mach-at91/include/mach/at91sam9263.h

 *

 * (C) 2007 Atmel Corporation.

 *

 * Common definitions.

 * Based on AT91SAM9263 datasheet revision B (Preliminary).

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91SAM9263_H

#define AT91SAM9263_H



/*

 * Peripheral identifiers/interrupts.

 */

#define AT91SAM9263_ID_PIOA	2	/* Parallel IO Controller A */

#define AT91SAM9263_ID_PIOB	3	/* Parallel IO Controller B */

#define AT91SAM9263_ID_PIOCDE	4	/* Parallel IO Controller C, D and E */

#define AT91SAM9263_ID_US0	7	/* USART 0 */

#define AT91SAM9263_ID_US1	8	/* USART 1 */

#define AT91SAM9263_ID_US2	9	/* USART 2 */

#define AT91SAM9263_ID_MCI0	10	/* Multimedia Card Interface 0 */

#define AT91SAM9263_ID_MCI1	11	/* Multimedia Card Interface 1 */

#define AT91SAM9263_ID_CAN	12	/* CAN */

#define AT91SAM9263_ID_TWI	13	/* Two-Wire Interface */

#define AT91SAM9263_ID_SPI0	14	/* Serial Peripheral Interface 0 */

#define AT91SAM9263_ID_SPI1	15	/* Serial Peripheral Interface 1 */

#define AT91SAM9263_ID_SSC0	16	/* Serial Synchronous Controller 0 */

#define AT91SAM9263_ID_SSC1	17	/* Serial Synchronous Controller 1 */

#define AT91SAM9263_ID_AC97C	18	/* AC97 Controller */

#define AT91SAM9263_ID_TCB	19	/* Timer Counter 0, 1 and 2 */

#define AT91SAM9263_ID_PWMC	20	/* Pulse Width Modulation Controller */

#define AT91SAM9263_ID_EMAC	21	/* Ethernet */

#define AT91SAM9263_ID_2DGE	23	/* 2D Graphic Engine */

#define AT91SAM9263_ID_UDP	24	/* USB Device Port */

#define AT91SAM9263_ID_ISI	25	/* Image Sensor Interface */

#define AT91SAM9263_ID_LCDC	26	/* LCD Controller */

#define AT91SAM9263_ID_DMA	27	/* DMA Controller */

#define AT91SAM9263_ID_UHP	29	/* USB Host port */

#define AT91SAM9263_ID_IRQ0	30	/* Advanced Interrupt Controller (IRQ0) */

#define AT91SAM9263_ID_IRQ1	31	/* Advanced Interrupt Controller (IRQ1) */





/*

 * User Peripheral physical base addresses.

 */

#define AT91SAM9263_BASE_UDP		0xfff78000

#define AT91SAM9263_BASE_TCB0		0xfff7c000

#define AT91SAM9263_BASE_TC0		0xfff7c000

#define AT91SAM9263_BASE_TC1		0xfff7c040

#define AT91SAM9263_BASE_TC2		0xfff7c080

#define AT91SAM9263_BASE_MCI0		0xfff80000

#define AT91SAM9263_BASE_MCI1		0xfff84000

#define AT91SAM9263_BASE_TWI		0xfff88000

#define AT91SAM9263_BASE_US0		0xfff8c000

#define AT91SAM9263_BASE_US1		0xfff90000

#define AT91SAM9263_BASE_US2		0xfff94000

#define AT91SAM9263_BASE_SSC0		0xfff98000

#define AT91SAM9263_BASE_SSC1		0xfff9c000

#define AT91SAM9263_BASE_AC97C		0xfffa0000

#define AT91SAM9263_BASE_SPI0		0xfffa4000

#define AT91SAM9263_BASE_SPI1		0xfffa8000

#define AT91SAM9263_BASE_CAN		0xfffac000

#define AT91SAM9263_BASE_PWMC		0xfffb8000

#define AT91SAM9263_BASE_EMAC		0xfffbc000

#define AT91SAM9263_BASE_ISI		0xfffc4000

#define AT91SAM9263_BASE_2DGE		0xfffc8000



/*

 * System Peripherals

 */

#define AT91SAM9263_BASE_ECC0	0xffffe000

#define AT91SAM9263_BASE_SDRAMC0 0xffffe200

#define AT91SAM9263_BASE_SMC0	0xffffe400

#define AT91SAM9263_BASE_ECC1	0xffffe600

#define AT91SAM9263_BASE_SDRAMC1 0xffffe800

#define AT91SAM9263_BASE_SMC1	0xffffea00

#define AT91SAM9263_BASE_MATRIX	0xffffec00

#define AT91SAM9263_BASE_DBGU	AT91_BASE_DBGU1

#define AT91SAM9263_BASE_PIOA	0xfffff200

#define AT91SAM9263_BASE_PIOB	0xfffff400

#define AT91SAM9263_BASE_PIOC	0xfffff600

#define AT91SAM9263_BASE_PIOD	0xfffff800

#define AT91SAM9263_BASE_PIOE	0xfffffa00

#define AT91SAM9263_BASE_RSTC	0xfffffd00

#define AT91SAM9263_BASE_SHDWC	0xfffffd10

#define AT91SAM9263_BASE_RTT0	0xfffffd20

#define AT91SAM9263_BASE_PIT	0xfffffd30

#define AT91SAM9263_BASE_WDT	0xfffffd40

#define AT91SAM9263_BASE_RTT1	0xfffffd50

#define AT91SAM9263_BASE_GPBR	0xfffffd60



#define AT91_SMC	AT91_SMC0



/*

 * Internal Memory.

 */

#define AT91SAM9263_SRAM0_BASE	0x00300000	/* Internal SRAM 0 base address */

#define AT91SAM9263_SRAM0_SIZE	(80 * SZ_1K)	/* Internal SRAM 0 size (80Kb) */



#define AT91SAM9263_ROM_BASE	0x00400000	/* Internal ROM base address */

#define AT91SAM9263_ROM_SIZE	SZ_128K		/* Internal ROM size (128Kb) */



#define AT91SAM9263_SRAM1_BASE	0x00500000	/* Internal SRAM 1 base address */

#define AT91SAM9263_SRAM1_SIZE	SZ_16K		/* Internal SRAM 1 size (16Kb) */



#define AT91SAM9263_LCDC_BASE	0x00700000	/* LCD Controller */

#define AT91SAM9263_DMAC_BASE	0x00800000	/* DMA Controller */

#define AT91SAM9263_UHP_BASE	0x00a00000	/* USB Host controller */





#endif

arch/arm/mach-at91/include/mach/at91sam9g45.h

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/*

 * Chip-specific header file for the AT91SAM9G45 family

 *

 *  Copyright (C) 2008-2009 Atmel Corporation.

 *

 * Common definitions.

 * Based on AT91SAM9G45 preliminary datasheet.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation; either version 2 of the License, or

 * (at your option) any later version.

 */



#ifndef AT91SAM9G45_H

#define AT91SAM9G45_H



/*

 * Peripheral identifiers/interrupts.

 */

#define AT91SAM9G45_ID_PIOA	2	/* Parallel I/O Controller A */

#define AT91SAM9G45_ID_PIOB	3	/* Parallel I/O Controller B */

#define AT91SAM9G45_ID_PIOC	4	/* Parallel I/O Controller C */

#define AT91SAM9G45_ID_PIODE	5	/* Parallel I/O Controller D and E */

#define AT91SAM9G45_ID_TRNG	6	/* True Random Number Generator */

#define AT91SAM9G45_ID_US0	7	/* USART 0 */

#define AT91SAM9G45_ID_US1	8	/* USART 1 */

#define AT91SAM9G45_ID_US2	9	/* USART 2 */

#define AT91SAM9G45_ID_US3	10	/* USART 3 */

#define AT91SAM9G45_ID_MCI0	11	/* High Speed Multimedia Card Interface 0 */

#define AT91SAM9G45_ID_TWI0	12	/* Two-Wire Interface 0 */

#define AT91SAM9G45_ID_TWI1	13	/* Two-Wire Interface 1 */

#define AT91SAM9G45_ID_SPI0	14	/* Serial Peripheral Interface 0 */

#define AT91SAM9G45_ID_SPI1	15	/* Serial Peripheral Interface 1 */

#define AT91SAM9G45_ID_SSC0	16	/* Synchronous Serial Controller 0 */

#define AT91SAM9G45_ID_SSC1	17	/* Synchronous Serial Controller 1 */

#define AT91SAM9G45_ID_TCB	18	/* Timer Counter 0, 1, 2, 3, 4 and 5 */

#define AT91SAM9G45_ID_PWMC	19	/* Pulse Width Modulation Controller */

#define AT91SAM9G45_ID_TSC	20	/* Touch Screen ADC Controller */

#define AT91SAM9G45_ID_DMA	21	/* DMA Controller */

#define AT91SAM9G45_ID_UHPHS	22	/* USB Host High Speed */

#define AT91SAM9G45_ID_LCDC	23	/* LCD Controller */

#define AT91SAM9G45_ID_AC97C	24	/* AC97 Controller */

#define AT91SAM9G45_ID_EMAC	25	/* Ethernet MAC */

#define AT91SAM9G45_ID_ISI	26	/* Image Sensor Interface */

#define AT91SAM9G45_ID_UDPHS	27	/* USB Device High Speed */

#define AT91SAM9G45_ID_AESTDESSHA 28	/* AES + T-DES + SHA */

#define AT91SAM9G45_ID_MCI1	29	/* High Speed Multimedia Card Interface 1 */

#define AT91SAM9G45_ID_VDEC	30	/* Video Decoder */

#define AT91SAM9G45_ID_IRQ0	31	/* Advanced Interrupt Controller */



/*

 * User Peripheral physical base addresses.

 */

#define AT91SAM9G45_BASE_UDPHS		0xfff78000

#define AT91SAM9G45_BASE_TCB0		0xfff7c000

#define AT91SAM9G45_BASE_TC0		0xfff7c000

#define AT91SAM9G45_BASE_TC1		0xfff7c040

#define AT91SAM9G45_BASE_TC2		0xfff7c080

#define AT91SAM9G45_BASE_MCI0		0xfff80000

#define AT91SAM9G45_BASE_TWI0		0xfff84000

#define AT91SAM9G45_BASE_TWI1		0xfff88000

#define AT91SAM9G45_BASE_US0		0xfff8c000

#define AT91SAM9G45_BASE_US1		0xfff90000

#define AT91SAM9G45_BASE_US2		0xfff94000

#define AT91SAM9G45_BASE_US3		0xfff98000

#define AT91SAM9G45_BASE_SSC0		0xfff9c000

#define AT91SAM9G45_BASE_SSC1		0xfffa0000

#define AT91SAM9G45_BASE_SPI0		0xfffa4000

#define AT91SAM9G45_BASE_SPI1		0xfffa8000

#define AT91SAM9G45_BASE_AC97C		0xfffac000

#define AT91SAM9G45_BASE_TSC		0xfffb0000

#define AT91SAM9G45_BASE_ISI		0xfffb4000

#define AT91SAM9G45_BASE_PWMC		0xfffb8000

#define AT91SAM9G45_BASE_EMAC		0xfffbc000

#define AT91SAM9G45_BASE_AES		0xfffc0000

#define AT91SAM9G45_BASE_TDES		0xfffc4000

#define AT91SAM9G45_BASE_SHA		0xfffc8000

#define AT91SAM9G45_BASE_TRNG		0xfffcc000

#define AT91SAM9G45_BASE_MCI1		0xfffd0000

#define AT91SAM9G45_BASE_TCB1		0xfffd4000

#define AT91SAM9G45_BASE_TC3		0xfffd4000

#define AT91SAM9G45_BASE_TC4		0xfffd4040

#define AT91SAM9G45_BASE_TC5		0xfffd4080



/*

 * System Peripherals

 */

#define AT91SAM9G45_BASE_ECC	0xffffe200

#define AT91SAM9G45_BASE_DDRSDRC1 0xffffe400

#define AT91SAM9G45_BASE_DDRSDRC0 0xffffe600

#define AT91SAM9G45_BASE_DMA	0xffffec00

#define AT91SAM9G45_BASE_SMC	0xffffe800

#define AT91SAM9G45_BASE_MATRIX	0xffffea00

#define AT91SAM9G45_BASE_DBGU	AT91_BASE_DBGU1

#define AT91SAM9G45_BASE_PIOA	0xfffff200

#define AT91SAM9G45_BASE_PIOB	0xfffff400

#define AT91SAM9G45_BASE_PIOC	0xfffff600

#define AT91SAM9G45_BASE_PIOD	0xfffff800

#define AT91SAM9G45_BASE_PIOE	0xfffffa00

#define AT91SAM9G45_BASE_RSTC	0xfffffd00

#define AT91SAM9G45_BASE_SHDWC	0xfffffd10

#define AT91SAM9G45_BASE_RTT	0xfffffd20

#define AT91SAM9G45_BASE_PIT	0xfffffd30

#define AT91SAM9G45_BASE_WDT	0xfffffd40

#define AT91SAM9G45_BASE_RTC	0xfffffdb0

#define AT91SAM9G45_BASE_GPBR	0xfffffd60



/*

 * Internal Memory.

 */

#define AT91SAM9G45_SRAM_BASE	0x00300000	/* Internal SRAM base address */

#define AT91SAM9G45_SRAM_SIZE	SZ_64K		/* Internal SRAM size (64Kb) */



#define AT91SAM9G45_ROM_BASE	0x00400000	/* Internal ROM base address */

#define AT91SAM9G45_ROM_SIZE	SZ_64K		/* Internal ROM size (64Kb) */



#define AT91SAM9G45_LCDC_BASE	0x00500000	/* LCD Controller */

#define AT91SAM9G45_UDPHS_FIFO	0x00600000	/* USB Device HS controller */

#define AT91SAM9G45_OHCI_BASE	0x00700000	/* USB Host controller (OHCI) */

#define AT91SAM9G45_EHCI_BASE	0x00800000	/* USB Host controller (EHCI) */

#define AT91SAM9G45_VDEC_BASE	0x00900000	/* Video Decoder Controller */



/*

 * DMA peripheral identifiers

 * for hardware handshaking interface

 */

#define AT_DMA_ID_MCI0		 0

#define AT_DMA_ID_SPI0_TX	 1

#define AT_DMA_ID_SPI0_RX	 2

#define AT_DMA_ID_SPI1_TX	 3

#define AT_DMA_ID_SPI1_RX	 4

#define AT_DMA_ID_SSC0_TX	 5

#define AT_DMA_ID_SSC0_RX	 6

#define AT_DMA_ID_SSC1_TX	 7

#define AT_DMA_ID_SSC1_RX	 8

#define AT_DMA_ID_AC97_TX	 9

#define AT_DMA_ID_AC97_RX	10

#define AT_DMA_ID_AES_TX	11

#define AT_DMA_ID_AES_RX	12

#define AT_DMA_ID_MCI1		13



#endif