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Commit 4c4925c1 authored Jun 11, 2008 by Nicolas Pitre Committed by Lennert Buytenhek Jun 22, 2008

[ARM] fix cache alignment code in memset.S



This code is currently disabled, which explains why no one was affected.

Signed-off-by: Nicolas Pitre <nico@marvell.com>
Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

parent f76e9154

arch/arm/lib/memmove.S

+1 −1

Original line number	Diff line number	Diff line
		@@ -60,6 +60,7 @@ ENTRY(memmove)
		CALGN( bcs 2f )
		CALGN( adr r4, 6f )
		CALGN( subs r2, r2, ip ) @ C is set here
		CALGN( rsb ip, ip, #32 )
		CALGN( add pc, r4, ip )

		PLD( pld [r1, #-4] )
		@@ -139,7 +140,6 @@ ENTRY(memmove)
		blt 14f

		CALGN( ands ip, r1, #31 )
		CALGN( rsb ip, ip, #32 )
		CALGN( sbcnes r4, ip, r2 ) @ C is always set here
		CALGN( subcc r2, r2, ip )
		CALGN( bcc 15f )