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Commit 4c43e0d0 authored by Tomas Winkler's avatar Tomas Winkler Committed by John W. Linville
Browse files

iwlwifi: HW bug fixes



This patch adds few HW bug fixes.

Signed-off-by: default avatarTomas Winkler <tomas.winkler@intel.com>
Signed-off-by: default avatarZhu Yi <yi.zhu@intel.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent 6041e2a0
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+15 −0
Original line number Original line Diff line number Diff line
@@ -93,6 +93,13 @@ static int iwl5000_apm_init(struct iwl_priv *priv)
	iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
	iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
		    CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);


	/* Set FH wait treshold to maximum (HW error during stress W/A) */
	iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);

	/* enable HAP INTA to move device L1a -> L0s */
	iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
		    CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);

	iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
	iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);


	/* set "initialization complete" bit to move adapter
	/* set "initialization complete" bit to move adapter
@@ -230,6 +237,14 @@ static void iwl5000_nic_config(struct iwl_priv *priv)
		    CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
		    CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
		    CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
		    CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);


	/* W/A : NIC is stuck in a reset state after Early PCIe power off
	 * (PCIe power is lost before PERST# is asserted),
	 * causing ME FW to lose ownership and not being able to obtain it back.
	 */
	 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
				APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
				~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);

	spin_unlock_irqrestore(&priv->lock, flags);
	spin_unlock_irqrestore(&priv->lock, flags);
}
}


+9 −1
Original line number Original line Diff line number Diff line
@@ -104,6 +104,7 @@
 *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
 *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
 */
 */
#define CSR_HW_REV_WA_REG	(CSR_BASE+0x22C)
#define CSR_HW_REV_WA_REG	(CSR_BASE+0x22C)
#define CSR_DBG_HPET_MEM_REG	(CSR_BASE+0x240)


/* Bits for CSR_HW_IF_CONFIG_REG */
/* Bits for CSR_HW_IF_CONFIG_REG */
#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R	(0x00000010)
#define CSR49_HW_IF_CONFIG_REG_BIT_4965_R	(0x00000010)
@@ -118,7 +119,12 @@
#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A    (0x00000000)
#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)
#define CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B    (0x00001000)


#define CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A		(0x00080000)
#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM		(0x00200000)
#define CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM		(0x00200000)
#define CSR_HW_IF_CONFIG_REG_BIT_PCI_OWN_SEM		(0x00400000)
#define CSR_HW_IF_CONFIG_REG_BIT_ME_OWN			(0x02000000)
#define CSR_HW_IF_CONFIG_REG_BIT_WAKE_ME		(0x08000000)



/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
 * acknowledged (reset) by host writing "1" to flagged bits. */
 * acknowledged (reset) by host writing "1" to flagged bits. */
@@ -236,6 +242,8 @@
#define CSR39_ANA_PLL_CFG_VAL        (0x01000000)
#define CSR39_ANA_PLL_CFG_VAL        (0x01000000)
#define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
#define CSR50_ANA_PLL_CFG_VAL        (0x00880300)


/* HPET MEM debug */
#define CSR_DBG_HPET_MEM_REG_VAL	(0xFFFF0000)
/*=== HBUS (Host-side Bus) ===*/
/*=== HBUS (Host-side Bus) ===*/
#define HBUS_BASE	(0x400)
#define HBUS_BASE	(0x400)
/*
/*
+7 −5
Original line number Original line Diff line number Diff line
@@ -84,14 +84,16 @@
#define APMG_CLK_VAL_DMA_CLK_RQT	(0x00000200)
#define APMG_CLK_VAL_DMA_CLK_RQT	(0x00000200)
#define APMG_CLK_VAL_BSM_CLK_RQT	(0x00000800)
#define APMG_CLK_VAL_BSM_CLK_RQT	(0x00000800)


#define APMG_PS_CTRL_VAL_RESET_REQ	(0x04000000)

#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS	(0x00000800)


#define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS	(0x00400000)
#define APMG_PS_CTRL_VAL_RESET_REQ		(0x04000000)
#define APMG_PS_CTRL_MSK_PWR_SRC		(0x03000000)
#define APMG_PS_CTRL_MSK_PWR_SRC		(0x03000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN		(0x00000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN		(0x00000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX         (0x01000000)
#define APMG_PS_CTRL_VAL_PWR_SRC_MAX		(0x01000000) /* 3945 only */
#define APMG_PS_CTRL_VAL_PWR_SRC_VAUX		(0x02000000)



#define APMG_PCIDEV_STT_VAL_L1_ACT_DIS		(0x00000800)


/**
/**
 * BSM (Bootstrap State Machine)
 * BSM (Bootstrap State Machine)
+1 −1
Original line number Original line Diff line number Diff line
@@ -3920,7 +3920,7 @@ void ieee80211_scan_completed(struct ieee80211_hw *hw)
	if (sdata->vif.type == IEEE80211_IF_TYPE_IBSS) {
	if (sdata->vif.type == IEEE80211_IF_TYPE_IBSS) {
		struct ieee80211_if_sta *ifsta = &sdata->u.sta;
		struct ieee80211_if_sta *ifsta = &sdata->u.sta;
		if (!(ifsta->flags & IEEE80211_STA_BSSID_SET) ||
		if (!(ifsta->flags & IEEE80211_STA_BSSID_SET) ||
		    (!ifsta->state == IEEE80211_IBSS_JOINED &&
		    (!(ifsta->state == IEEE80211_IBSS_JOINED) &&
		    !ieee80211_sta_active_ibss(dev)))
		    !ieee80211_sta_active_ibss(dev)))
			ieee80211_sta_find_ibss(dev, ifsta);
			ieee80211_sta_find_ibss(dev, ifsta);
	}
	}