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Commit 4c2cedeb authored by Sankaran Nampoothiri's avatar Sankaran Nampoothiri Committed by Avinash Philip
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drivers: llcc_perfmon: Add llcc_perfmon support 



This is snapshot of the llcc_perfmon driver from msm-4.14
'commit c9961d61d6d8 ("drivers: soc: llcc_perfmon: Add llcc_perfmon
		support")'

This LLCC perfmon driver provides Sysfs interfaces for the clients to
monitor the events. Driver support for monitor events from LLCC sub blocks.
Also updated driver to handle opcode & cache alloc filters.

Change-Id: Ic711fdbc774d2da1938feff5c0d7888e5cf8495a
Signed-off-by: default avatarSankaran Nampoothiri <snampoot@codeaurora.org>
Signed-off-by: default avatarAvinash Philip <avinashp@codeaurora.org>
parent 60450b0d

drivers/soc/qcom/Kconfig

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Original line number Diff line number Diff line
@@ -90,6 +90,16 @@ config QCOM_SDM845_LLCC 
	  data required to configure LLCC so that clients can start using the

	  LLCC slices.



config QCOM_LLCC_PERFMON

	tristate "Qualcomm Technologies, Inc. LLCC Perfmon driver"

	depends on QCOM_LLCC

	help

	  This option enables driver for LLCC Performance monitor block. Using

	  this various events in different LLCC sub ports can be monitored.

	  This is used for performance and debug activity and exports sysfs

	  interface. sysfs interface is used to configure and dump the LLCC

	  performance events.



config QCOM_MDT_LOADER

	tristate

	select QCOM_SCM

drivers/soc/qcom/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -33,6 +33,7 @@ obj-$(CONFIG_QCOM_APR) += apr.o 
obj-$(CONFIG_QCOM_LLCC) += llcc-slice.o

obj-$(CONFIG_QCOM_LAHAINA_LLCC) += llcc-lahaina.o

obj-$(CONFIG_QCOM_SDM845_LLCC) += llcc-sdm845.o

obj-$(CONFIG_QCOM_LLCC_PERFMON) += llcc_perfmon.o

obj-$(CONFIG_QCOM_RPMHPD) += rpmhpd.o

obj-$(CONFIG_QCOM_RPMPD) += rpmpd.o

obj-$(CONFIG_QMP_DEBUGFS_CLIENT) += qmp-debugfs-client.o

drivers/soc/qcom/llcc_events.h

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Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _SOC_QCOM_LLCC_EVENTS_H_

#define _SOC_QCOM_LLCC_EVENTS_H_



enum event_port_select {

	EVENT_PORT_FEAC,

	EVENT_PORT_FERC,

	EVENT_PORT_FEWC,

	EVENT_PORT_BEAC,

	EVENT_PORT_BERC,

	EVENT_PORT_TRP,

	EVENT_PORT_DRP,

	EVENT_PORT_PMGR,

	EVENT_PORT_TENURE,

	EVENT_PORT_TLAT,

};



enum feac_events {

	FEAC_ANY_ACCESS,

	FEAC_READ_INCR,

	FEAC_WRITE_INCR,

	FEAC_WRITE_ORDERED,

	FEAC_READE_EXCL,

	FEAC_WRITE_EXCL,

	FEAC_CMO,

	FEAC_CMO_CLEAN,

	FEAC_CMO_INVAL,

	FEAC_CMO_CLEANINVAL,

	FEAC_CMO_DCPLD,

	FEAC_READ_NOALLOC,

	FEAC_WRITE_NOALLOC,

	FEAC_PREFETCH,

	FEAC_RD_BYTES,

	FEAC_RD_BEATS,

	FEAC_WR_BYTES,

	FEAC_WR_BEATS,

	FEAC_FC_READ,

	FEAC_EWD_ACCESS,

	FEAC_TCM_ACCESS,

	FEAC_GM_HIT,

	FEAC_GM_MISS,

	FEAC_GM_UNAVAILABLE,

	FEAC_XPU_ERROR,

	FEAC_READ_HAZARD,

	FEAC_WRITE_HAZARD,

	FEAC_GRANULE_READ,

	FEAC_GRANULE_WRITE,

	FEAC_RIFB_ALLOC,

	FEAC_WIFB_ALLOC,

	FEAC_RIFB_DEALLOC,

	FEAC_WIFB_DEALLOC,

	FEAC_RESERVED,

	FEAC_RESERVED1,

	FEAC_FEAC2TRP_LP_TX,

	FEAC_TRP_LP_BUSY,

	FEAC_FEAC2TRP_HP_TX,

	FEAC_TRP_HP_BUSY,

	FEAC_FEAC2FEWC_TX,

	FEAC_BEAC_LP_BUSY,

	FEAC_BEAC_HP_BUSY,

	FEAC_RIFB_FULL,

	FEAC_WIFB_FULL,

	FEAC_RD_CRDT_TX,

	FEAC_WR_CRDT_TX,

	FEAC_PROMOTION,

	FEAC_FEAC2TRP_LP_PRESSURE,

	FEAC_FEAC2TRP_HP_PRESSURE,

	FEAC_FEAC2FEWC_PRESSURE,

	FEAC_FEAC2BEAC_LP_PRESSURE,

	FEAC_FEAC2BEAC_HP_PRESSURE,

	FEAC_WR_THROUGH,

};



enum ferc_events {

	FERC_BERC_CMD,

	FERC_BERC_BEAT,

	FERC_DRP_CMD,

	FERC_DRP_BEAT,

	FERC_RD_CTRL_RSP_TX,

	FERC_WR_CTRL_RSP_TX,

	FERC_RD_DATA_TX,

	FERC_MISS_TRUMPS_HIT,

	FERC_HIT_TRUMPS_WRSP,

	FERC_RD_INTRA_RSP_IDLE,

};



enum fewc_events {

	FEWC_WR_CMD,

	FEWC_WR_DATA_BEAT,

	FEWC_WR_LAST,

	FEWC_WBUF_DEALLOC,

	FEWC_WR_HIT,

	FEWC_WR_MISS,

	FEWC_NC_RMW,

	FEWC_WR_DOWNGRADE,

	FEWC_BEAC_WR_CMD,

	FEWC_BEAC_WR_BEAT,

	FEWC_BEAC_RD_CMD,

	FEWC_BERC_FILL_BEAT,

	FEWC_DRP_WR_CMD,

	FEWC_DRP_WR_BEAT,

	FEWC_DRP_RD_BEAT,

	FEWC_TRP_TAG_LOOKUP,

	FEWC_TRP_TAG_UPDATE,

	FEWC_TRP_UNSTALL,

	FEWC_WBUFFS_FULL,

	FEWC_DRP_BUSY,

	FEWC_BEAC_WR_BUSY,

	FEWC_BEAC_RD_BUSY,

	FEWC_TRP_TAG_LOOKUP_BUSY,

	FEWC_TRP_TAG_UPDATE_BUSY,

	FEWC_C_RMW,

	FEWC_NC_ALLOC_RMW,

	FEWC_NC_NO_ALLOC_RMW,

	FEWC_NC_RMW_DEALLOC,

	FEWC_C_RMW_DEALLOC,

	FEWC_STALLED_BY_EVICT,

};



enum beac_events {

	BEAC_RD_TX,

	BEAC_WR_TX,

	BEAC_RD_GRANULE,

	BEAC_WR_GRANULE,

	BEAC_WR_BEAT_TX,

	BEAC_RD_CRDT_ZERO,

	BEAC_WR_CRDT_ZERO,

	BEAC_WDATA_CRDT_ZERO,

	BEAC_IFCMD_CRDT_ZERO,

	BEAC_IFWDATA_CRDT_ZERO,

	BEAC_PCT_ENTRY_ALLOC,

	BEAC_PCT_ENTRY_FREE,

	BEAC_PCT_FULL,

	BEAC_RD_PROMOTION_TX,

	BEAC_WR_PROMOTION_TX,

	BEAC_RD_PRESSURE_TX,

	BEAC_WR_PRESSURE_TX,

};



enum berc_events {

	BERC_RD_CMD,

	BERC_ERROR_CMD,

	BERC_PCT_ENTRY_DEALLOC,

	BERC_RD_RSP_RX,

	BERC_RD_RSP_BEAT_RX,

	BERC_RD_LA_RX,

	BERC_UNSTALL_RX,

	BERC_TX_RD_CMD,

	BERC_TX_ERR_CMD,

	BERC_TX_RD_BEAT,

	BERC_TX_ERR_BEAT,

	BERC_RESERVED,

	BERC_RESERVED1,

	BERC_CMO_RX,

	BERC_CMO_TX,

	BERC_DRP_WR_TX,

	BERC_DRP_WR_BEAT_TX,

	BERC_FEWC_WR_TX,

	BERC_FEWC_WR_BEAT_TX,

	BERC_LBUFFS_FULL,

	BERC_DRP_BUSY,

	BERC_FEWC_BUSY,

	BERC_LBUFF_STALLED,

};



enum trp_events {

	TRP_ANY_ACCESS,

	TRP_INCR_RD,

	TRP_INCR_WR,

	TRP_ANY_HIT,

	TRP_RD_HIT,

	TRP_WR_HIT,

	TRP_RD_MISS,

	TRP_WR_MISS,

	TRP_RD_HIT_MISS,

	TRP_WR_HIT_MISS,

	TRP_EVICT,

	TRP_GRANULE_EVICT,

	TRP_RD_EVICT,

	TRP_WR_EVICT,

	TRP_LINE_FILL,

	TRP_GRANULE_FILL,

	TRP_WSC_WRITE,

	TRP_WSC_EVICT,

	TRP_SUBCACHE_ACT,

	TRP_SUBCACHE_DEACT,

	TRP_RD_DEACTIVE_SUBCACHE,

	TRP_WR_DEACTIVE_SUBCACHE,

	TRP_INVALID_LINE_ALLOC,

	TRP_DEACTIVE_LINE_ALLOC,

	TRP_SELF_EVICTION_ALLOC,

	TRP_UC_SUBCACHE_ALLOC,

	TRP_FC_SELF_EVICTION_ALLOC,

	TRP_LP_SUBCACHE_VICTIM,

	TRP_OC_SUBCACHE_VICTIM,

	TRP_MRU_ROLLOVER,

	TRP_NC_DOWNGRADE,

	TRP_TAGRAM_CORR_ERR,

	TRP_TAGRAM_UNCORR_ERR,

	TRP_RD_MISS_FC,

	TRP_CPU_WRITE_EWD_LINE,

	TRP_CLIENT_WRITE_EWD_LINE,

	TRP_CLIENT_READ_EWD_LINE,

	TRP_CMO_I_EWD_LINE,

	TRP_CMO_I_DIRTY_LINE,

	TRP_DRP_RD_NOTIFICATION,

	TRP_DRP_WR_NOTIFICATION,

	TRP_LINEFILL_TAG_UPDATE,

	TRP_FEWC_TAG_UPDATE,

	TRP_ET_FULL,

	TRP_NAWT_FULL,

	TRP_HITQ_FULL,

	TRP_ET_ALLOC,

	TRP_ET_DEALLOC,

	TRP_NAWT_ALLOC,

	TRP_NAWT_DEALLOC,

	TRP_RD_REPLAY,

	TRP_WR_ECC_RD,

	TRP_ET_LP_FULL,

	TRP_ET_HP_FULL,

	TRP_SOEH,

};



enum drp_events {

	DRP_TRP_RD_NOTIFICATION,

	DRP_TRP_WR_NOTIFICATION,

	DRP_BIST_WR_NOTIFICATION,

	DRP_DRIE_WR_NOTIFICATION,

	DRP_ECC_CORR_ERR,

	DRP_ECC_UNCORR_ERR,

	DRP_FERC_RD_TX,

	DRP_FEWC_RD_TX,

	DRP_EVICT_LINE_TX,

	DRP_EVICT_GRANULE_TX,

	DRP_BIST_TX,

	DRP_FERC_RD_BEAT,

	DRP_FEWC_RD_BEAT,

	DRP_BIST_RD_BEAT,

	DRP_EVICT_RD_BEAT,

	DRP_BERC_WR_BEAT,

	DRP_FEWC_WR_BEAT,

	DRP_BIST_WR_BEAT,

	DRP_DRIE_WR_BEAT,

	DRP_BERC_UNSTALL,

	DRP_FEWC_UNSTALL,

	DRP_LB_RD,

	DRP_LB_WR,

	DRP_BANK_CONFLICT,

	DRP_FILL_TRUMPS_RD,

	DRP_RD_TRUMPS_WR,

	DRP_LB_SLP_RET,

	DRP_LB_SLP_NRET,

	DRP_LB_WAKEUP,

	DRP_TRP_EARLY_WAKEUP,

	DRP_PCB_IDLE,

	DRP_EVICT_RDFIFO_FULL,

	DRP_FEWC_RDFIFO_FULL,

	DRP_FERC_RDFIFO_FULL,

	DRP_FERC_RD,

	DRP_FEWC_RD,

	DRP_LINE_EVICT,

	DRP_GRANULE_EVICT,

	DRP_BIST_RD,

	DRP_FEWC_WR,

	DRP_LINE_FILL,

	DRP_GRANULE_FILL,

	DRP_BIST_WR,

	DRP_DRIE_WR,

};



enum pmgr_events {

	PMGR_Q_RUN_STATE,

	PMGR_Q_DENIED_STATE,

	PMGR_Q_STOPEED_TO_Q_RUN,

	PMGR_Q_RUN_TO_Q_FENCED,

	PMGR_Q_RUN_TO_Q_DENIED,

	PMGR_Q_DENIED_TO_Q_RUN,

	PMGR_Q_FENCED_TO_Q_STOPPED,

	PMGR_Q_FENCED_TO_Q_DENIED,

};



enum filter_type {

	SCID,

	MID,

	PROFILING_TAG,

	WAY_ID,

	OPCODE,

	CACHEALLOC,

	UNKNOWN,

};



#endif /* _SOC_QCOM_LLCC_EVENTS_H_ */

drivers/soc/qcom/llcc_perfmon.c

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File added.

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drivers/soc/qcom/llcc_perfmon.h

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/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2019, The Linux Foundation. All rights reserved.

 */



#ifndef _SOC_QCOM_LLCC_PERFMON_H_

#define _SOC_QCOM_LLCC_PERFMON_H_



#define LLCC_COMMON_HW_INFO		(0x30000)

#define LLCC_COMMON_STATUS0		(0x3000C)

/* FEAC */

#define FEAC_PROF_FILTER_0_CFG3		(0x03700C)

#define FEAC_PROF_FILTER_0_CFG5		(0x037014)

#define FEAC_PROF_FILTER_0_CFG6		(0x037018)

#define FEAC_PROF_EVENT_n_CFG(n)	(0x037060 + 4 * n)

#define FEAC_PROF_CFG			(0x0370A0)



/* FERC */

#define FERC_PROF_FILTER_0_CFG0		(0x03B000)

#define FERC_PROF_EVENT_n_CFG(n)	(0x03B020 + 4 * n)

#define FERC_PROF_CFG			(0x03B060)



/* FEWC */

#define FEWC_PROF_FILTER_0_CFG0		(0x033000)

#define FEWC_PROF_EVENT_n_CFG(n)	(0x033020 + 4 * n)



/* BEAC */

#define BEAC_PROF_FILTER_0_CFG5		(0x049014)

#define BEAC_PROF_EVENT_n_CFG(n)	(0x049040 + 4 * n)

#define BEAC_PROF_CFG			(0x049080)

#define BEAC_INST_OFF			(0x4000)



/* BERC */

#define BERC_PROF_FILTER_0_CFG0		(0x039000)

#define BERC_PROF_EVENT_n_CFG(n)	(0x039020 + 4 * n)

#define BERC_PROF_CFG			(0x039060)



/* TRP */

#define TRP_PROF_FILTER_0_CFG1		(0x024004)

#define TRP_PROF_EVENT_n_CFG(n)		(0x024020 + 4 * n)

#define TRP_SCID_n_STATUS(n)		(0x000004 + 0x1000 * n)



/* DRP */

#define DRP_PROF_EVENT_n_CFG(n)		(0x044010 + 4 * n)

#define DRP_PROF_CFG			(0x044050)



/* PMGR */

#define PMGR_PROF_EVENT_n_CFG(n)	(0x03F000 + 4 * n)



#define PERFMON_COUNTER_n_CONFIG(n)	(0x031020 + 4 * n)

#define PERFMON_MODE			(0x03100C)

#define PERFMON_DUMP			(0x031010)

#define BROADCAST_COUNTER_n_VALUE(n)	(0x031060 + 4 * n)



#define LLCC_COUNTER_n_VALUE(n)		(0x031060 + 4 * n)



#define EVENT_NUM_MAX			(64)

#define SCID_MAX			(32)



/* Perfmon */

#define CLEAR_ON_ENABLE			BIT(31)

#define CLEAR_ON_DUMP			BIT(30)

#define FREEZE_ON_SATURATE		BIT(29)

#define CHAINING_EN			BIT(28)

#define COUNT_CLOCK_EVENT		BIT(24)



#define EVENT_SELECT_SHIFT		(16)

#define PERFMON_EVENT_SELECT_MASK	GENMASK(EVENT_SELECT_SHIFT + 4,\

						EVENT_SELECT_SHIFT)

#define PORT_SELECT_SHIFT		(0)

#define PERFMON_PORT_SELECT_MASK	GENMASK(PORT_SELECT_SHIFT + 3,\

						PORT_SELECT_SHIFT)



#define MANUAL_MODE			(0)

#define TIMED_MODE			(1)

#define TRIGGER_MODE			(2)

#define MONITOR_EN_SHIFT		(15)

#define MONITOR_EN			BIT(MONITOR_EN_SHIFT)

#define PERFMON_MODE_MONITOR_EN_MASK	GENMASK(MONITOR_EN_SHIFT + 0,\

						MONITOR_EN_SHIFT)

#define MONITOR_MODE_SHIFT		(0)

#define PERFMON_MODE_MONITOR_MODE_MASK	GENMASK(MONITOR_MODE_SHIFT + 0,\

						MONITOR_MODE_SHIFT)



#define MONITOR_DUMP			BIT(0)



/* COMMON */

#define BYTE_SCALING			(1024)

#define BEAT_SCALING			(32)

#define LB_CNT_SHIFT			(28)

#define LB_CNT_MASK			GENMASK(LB_CNT_SHIFT + 3, \

						LB_CNT_SHIFT)

#define NUM_MC_SHIFT			(10)

#define NUM_MC_MASK			GENMASK(NUM_MC_SHIFT + 1, \

						NUM_MC_SHIFT)



#define BYTE_SCALING_SHIFT		(16)

#define PROF_CFG_BYTE_SCALING_MASK	GENMASK(BYTE_SCALING_SHIFT + 11,\

						BYTE_SCALING_SHIFT)

#define BEAT_SCALING_SHIFT		(8)

#define PROF_CFG_BEAT_SCALING_MASK	GENMASK(BEAT_SCALING_SHIFT + 7,\

						BEAT_SCALING_SHIFT)

#define PROF_EN_SHIFT			(0)

#define PROF_EN				BIT(PROF_EN_SHIFT)

#define PROF_CFG_EN_MASK		GENMASK(PROF_EN_SHIFT + 0,\

						PROF_EN_SHIFT)



#define FILTER_EN_SHIFT			(31)

#define FILTER_EN			BIT(FILTER_EN_SHIFT)

#define FILTER_EN_MASK			GENMASK(FILTER_EN_SHIFT + 0,\

						FILTER_EN_SHIFT)

#define FILTER_0			(0)

#define FILTER_0_MASK			GENMASK(FILTER_0 + 0, \

						FILTER_0)

#define FILTER_1			(1)

#define FILTER_1_MASK			GENMASK(FILTER_1 + 0, \

						FILTER_1)



#define FILTER_SEL_SHIFT		(16)

#define FILTER_SEL_MASK			GENMASK(FILTER_SEL_SHIFT + 0,\

						FILTER_SEL_SHIFT)

#define EVENT_SEL_SHIFT			(0)

#define EVENT_SEL_MASK			GENMASK(EVENT_SEL_SHIFT + 5,\

						EVENT_SEL_SHIFT)



#define CACHEALLOC_MASK_SHIFT		(16)

#define CACHEALLOC_MASK_MASK		GENMASK(CACHEALLOC_MASK_SHIFT + 3, \

					CACHEALLOC_MASK_SHIFT)

#define CACHEALLOC_MATCH_SHIFT		(12)

#define CACHEALLOC_MATCH_MASK		GENMASK(CACHEALLOC_MATCH_SHIFT + 3, \

					CACHEALLOC_MATCH_SHIFT)

#define OPCODE_MASK_SHIFT		(28)

#define OPCODE_MASK_MASK		GENMASK(OPCODE_MASK_SHIFT + 3, \

					OPCODE_MASK_SHIFT)

#define OPCODE_MATCH_SHIFT		(24)

#define OPCODE_MATCH_MASK		GENMASK(OPCODE_MATCH_SHIFT + 3, \

					OPCODE_MATCH_SHIFT)

#define MID_MASK_SHIFT			(16)

#define MID_MASK_MASK			GENMASK(MID_MASK_SHIFT + 15, \

						MID_MASK_SHIFT)

#define MID_MATCH_SHIFT			(0)

#define MID_MATCH_MASK			GENMASK(MID_MATCH_SHIFT + 15, \

						MID_MATCH_SHIFT)

#define SCID_MASK_SHIFT			(16)

#define SCID_MASK_MASK			GENMASK(SCID_MASK_SHIFT + 15, \

						SCID_MASK_SHIFT)

#define SCID_MATCH_SHIFT		(0)

#define SCID_MATCH_MASK			GENMASK(SCID_MATCH_SHIFT + 15, \

						SCID_MATCH_SHIFT)

#define SCID_MULTI_MATCH_SHIFT		(0)

#define SCID_MULTI_MATCH_MASK		GENMASK(SCID_MULTI_MATCH_SHIFT + 31, \

						SCID_MULTI_MATCH_SHIFT)

#define PROFTAG_MASK_SHIFT		(2)

#define PROFTAG_MASK_MASK		GENMASK(PROFTAG_MASK_SHIFT + 1,\

						PROFTAG_MASK_SHIFT)

#define PROFTAG_MATCH_SHIFT		(0)

#define PROFTAG_MATCH_MASK		GENMASK(PROFTAG_MATCH_SHIFT + 1,\

						PROFTAG_MATCH_SHIFT)

/* FEAC */

#define FEAC_SCALING_FILTER_SEL_SHIFT	(2)

#define FEAC_SCALING_FILTER_SEL_MASK	GENMASK(FEAC_SCALING_FILTER_SEL_SHIFT \

					+ 0, \

					FEAC_SCALING_FILTER_SEL_SHIFT)

#define FEAC_SCALING_FILTER_EN_SHIFT	(1)

#define FEAC_SCALING_FILTER_EN		BIT(FEAC_SCALING_FILTER_EN_SHIFT)

#define FEAC_SCALING_FILTER_EN_MASK	GENMASK(FEAC_SCALING_FILTER_EN_SHIFT \

					+ 0, \

					FEAC_SCALING_FILTER_EN_SHIFT)



#define FEAC_WR_BEAT_FILTER_SEL_SHIFT	(29)

#define FEAC_WR_BEAT_FILTER_SEL_MASK	GENMASK(FEAC_WR_BEAT_FILTER_SEL_SHIFT \

					+ 0, \

					FEAC_WR_BEAT_FILTER_SEL_SHIFT)

#define FEAC_WR_BEAT_FILTER_EN_SHIFT	(28)

#define FEAC_WR_BEAT_FILTER_EN_MASK	GENMASK(FEAC_WR_BEAT_FILTER_EN_SHIFT \

					+ 0, \

					FEAC_WR_BEAT_FILTER_EN_SHIFT)

#define FEAC_WR_BEAT_FILTER_EN		BIT(FEAC_WR_BEAT_FILTER_EN_SHIFT)

#define FEAC_WR_BYTE_FILTER_SEL_SHIFT	(6)

#define FEAC_WR_BYTE_FILTER_SEL_MASK	GENMASK(FEAC_WR_BYTE_FILTER_SEL_SHIFT \

					+ 0, \

					FEAC_WR_BYTE_FILTER_SEL_SHIFT)

#define FEAC_WR_BYTE_FILTER_EN_SHIFT	(5)

#define FEAC_WR_BYTE_FILTER_EN_MASK	GENMASK(FEAC_WR_BYTE_FILTER_EN_SHIFT \

					+ 0, \

					FEAC_WR_BYTE_FILTER_EN_SHIFT)

#define FEAC_WR_BYTE_FILTER_EN		BIT(FEAC_WR_BYTE_FILTER_EN_SHIFT)

#define FEAC_RD_BEAT_FILTER_SEL_SHIFT	(4)

#define FEAC_RD_BEAT_FILTER_SEL_MASK	GENMASK(FEAC_RD_BEAT_FILTER_SEL_SHIFT \

					+ 0, \

					FEAC_RD_BEAT_FILTER_SEL_SHIFT)

#define FEAC_RD_BEAT_FILTER_EN_SHIFT	(3)

#define FEAC_RD_BEAT_FILTER_EN_MASK	GENMASK(FEAC_RD_BEAT_FILTER_EN_SHIFT \

					+ 0, \

					FEAC_RD_BEAT_FILTER_EN_SHIFT)

#define FEAC_RD_BEAT_FILTER_EN		BIT(FEAC_RD_BEAT_FILTER_EN_SHIFT)

#define FEAC_RD_BYTE_FILTER_SEL_SHIFT	(2)

#define FEAC_RD_BYTE_FILTER_SEL_MASK	GENMASK(FEAC_RD_BYTE_FILTER_SEL_SHIFT \

					+ 0, \

					FEAC_RD_BYTE_FILTER_SEL_SHIFT)

#define FEAC_RD_BYTE_FILTER_EN_SHIFT	(1)

#define FEAC_RD_BYTE_FILTER_EN_MASK	GENMASK(FEAC_RD_BYTE_FILTER_EN_SHIFT \

					+ 0, \

					FEAC_RD_BYTE_FILTER_EN_SHIFT)

#define FEAC_RD_BYTE_FILTER_EN		BIT(FEAC_RD_BYTE_FILTER_EN_SHIFT)

/* BEAC */

#define BEAC_PROFTAG_MASK_SHIFT		(14)

#define BEAC_PROFTAG_MASK_MASK		GENMASK(BEAC_PROFTAG_MASK_SHIFT + 1,\

						BEAC_PROFTAG_MASK_SHIFT)

#define BEAC_PROFTAG_MATCH_SHIFT	(12)

#define BEAC_PROFTAG_MATCH_MASK		GENMASK(BEAC_PROFTAG_MATCH_SHIFT + 1,\

						BEAC_PROFTAG_MATCH_SHIFT)

#define BEAC_MC_PROFTAG_SHIFT		(1)

#define BEAC_MC_PROFTAG_MASK		GENMASK(BEAC_MC_PROFTAG_SHIFT + 1,\

					BEAC_MC_PROFTAG_SHIFT)

#define BEAC_WR_BEAT_FILTER_SEL_SHIFT	(6)

#define BEAC_WR_BEAT_FILTER_SEL_MASK	GENMASK(BEAC_WR_BEAT_FILTER_SEL_SHIFT \

					+ 0, \

					BEAC_WR_BEAT_FILTER_SEL_SHIFT)

#define BEAC_WR_BEAT_FILTER_EN_SHIFT	(5)

#define BEAC_WR_BEAT_FILTER_EN_MASK	GENMASK(BEAC_WR_BEAT_FILTER_EN_SHIFT \

					+ 0, \

					BEAC_WR_BEAT_FILTER_EN_SHIFT)

#define BEAC_WR_BEAT_FILTER_EN		BIT(BEAC_WR_BEAT_FILTER_EN_SHIFT)

#define BEAC_RD_BEAT_FILTER_SEL_SHIFT	(4)

#define BEAC_RD_BEAT_FILTER_SEL_MASK	GENMASK(BEAC_RD_BEAT_FILTER_SEL_SHIFT \

					+ 0, \

					BEAC_RD_BEAT_FILTER_SEL_SHIFT)

#define BEAC_RD_BEAT_FILTER_EN_SHIFT	(3)

#define BEAC_RD_BEAT_FILTER_EN_MASK	GENMASK(BEAC_RD_BEAT_FILTER_EN_SHIFT \

					+ 0, \

					BEAC_RD_BEAT_FILTER_EN_SHIFT)

#define BEAC_RD_BEAT_FILTER_EN		BIT(BEAC_RD_BEAT_FILTER_EN_SHIFT)

/* TRP */

#define TRP_SCID_MATCH_SHIFT		(0)

#define TRP_SCID_MATCH_MASK		GENMASK(TRP_SCID_MATCH_SHIFT + 4,\

						TRP_SCID_MATCH_SHIFT)

#define TRP_SCID_MASK_SHIFT		(8)

#define TRP_SCID_MASK_MASK		GENMASK(TRP_SCID_MASK_SHIFT + 4,\

						TRP_SCID_MASK_SHIFT)

#define TRP_WAY_ID_MATCH_SHIFT		(16)

#define TRP_WAY_ID_MATCH_MASK		GENMASK(TRP_WAY_ID_MATCH_SHIFT + 3,\

						TRP_WAY_ID_MATCH_SHIFT)

#define TRP_WAY_ID_MASK_SHIFT		(20)

#define TRP_WAY_ID_MASK_MASK		GENMASK(TRP_WAY_ID_MASK_SHIFT + 3,\

						TRP_WAY_ID_MASK_SHIFT)

#define TRP_PROFTAG_MATCH_SHIFT		(24)

#define TRP_PROFTAG_MATCH_MASK		GENMASK(TRP_PROFTAG_MATCH_SHIFT + 1,\

						TRP_PROFTAG_MATCH_SHIFT)

#define TRP_PROFTAG_MASK_SHIFT		(28)

#define TRP_PROFTAG_MASK_MASK		GENMASK(TRP_PROFTAG_MASK_SHIFT + 1,\

						TRP_PROFTAG_MASK_SHIFT)



#define TRP_SCID_STATUS_ACTIVE_SHIFT		(0)

#define TRP_SCID_STATUS_ACTIVE_MASK		GENMASK( \

						TRP_SCID_STATUS_ACTIVE_SHIFT \

						+ 0, \

						TRP_SCID_STATUS_ACTIVE_SHIFT)

#define TRP_SCID_STATUS_DEACTIVE_SHIFT		(1)

#define TRP_SCID_STATUS_CURRENT_CAP_SHIFT	(16)

#define TRP_SCID_STATUS_CURRENT_CAP_MASK	GENMASK( \

					TRP_SCID_STATUS_CURRENT_CAP_SHIFT \

					+ 13, \

					TRP_SCID_STATUS_CURRENT_CAP_SHIFT)



#define LLCC_VERSION			(0x01010100)

#define REV_0				(0x0)

#define REV_1				(0x1)

#define BANK_OFFSET			(0x80000)

#endif /* _SOC_QCOM_LLCC_PERFMON_H_ */