Loading asoc/codecs/wsa883x/wsa883x.c +3 −2 Original line number Diff line number Diff line Loading @@ -100,9 +100,10 @@ static const struct wsa_reg_mask_val reg_init[] = { {WSA883X_DRE_CTL_0, 0xF0, 0x90}, {WSA883X_DRE_IDLE_DET_CTL, 0x10, 0x00}, {WSA883X_PDM_WD_CTL, 0x01, 0x01}, {WSA883X_CURRENT_LIMIT, 0x78, 0x40}, {WSA883X_CURRENT_LIMIT, 0x78, 0x20}, {WSA883X_DRE_CTL_0, 0x07, 0x02}, {WSA883X_VAGC_TIME, 0x03, 0x02}, {WSA883X_VAGC_TIME, 0x0F, 0x0F}, {WSA883X_VAGC_ATTN_LVL_3, 0x07, 0x02}, {WSA883X_VAGC_CTL, 0x01, 0x01}, {WSA883X_TAGC_CTL, 0x0E, 0x0A}, {WSA883X_TAGC_TIME, 0x0C, 0x0C}, Loading Loading
asoc/codecs/wsa883x/wsa883x.c +3 −2 Original line number Diff line number Diff line Loading @@ -100,9 +100,10 @@ static const struct wsa_reg_mask_val reg_init[] = { {WSA883X_DRE_CTL_0, 0xF0, 0x90}, {WSA883X_DRE_IDLE_DET_CTL, 0x10, 0x00}, {WSA883X_PDM_WD_CTL, 0x01, 0x01}, {WSA883X_CURRENT_LIMIT, 0x78, 0x40}, {WSA883X_CURRENT_LIMIT, 0x78, 0x20}, {WSA883X_DRE_CTL_0, 0x07, 0x02}, {WSA883X_VAGC_TIME, 0x03, 0x02}, {WSA883X_VAGC_TIME, 0x0F, 0x0F}, {WSA883X_VAGC_ATTN_LVL_3, 0x07, 0x02}, {WSA883X_VAGC_CTL, 0x01, 0x01}, {WSA883X_TAGC_CTL, 0x0E, 0x0A}, {WSA883X_TAGC_TIME, 0x0C, 0x0C}, Loading