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Commit 4bd2d9a3 authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "power: supply: qcom: Add support PM5100 in smblite"

parents 8bb974aa 41ed6d6f

drivers/power/supply/qcom/qpnp-smblite.c

+127 −44
Original line number Diff line number Diff line
@@ -25,51 +25,104 @@ 


static struct power_supply_desc usb_psy_desc;



static struct smb_params smblite_params = {

static const struct smb_base_address smb_base[] = {

	[PM2250] = {

		.chg_base   = 0x1000,

		.dcdc_base  = 0x1100,

		.batif_base = 0x1200,

		.usbin_base = 0x1300,

		.misc_base  = 0x1600,

		.typec_base = 0x1500,

	},



	[PM5100] = {

		.chg_base   = 0x2600,

		.batif_base = 0x2800,

		.usbin_base = 0x2900,

		.misc_base  = 0x2c00,

		.dcdc_base  = 0x2700,

	},

};



static struct smb_params smblite_pm2250_params = {

	.fcc			= {

		.name   = "fast charge current",

		.reg    = CHGR_FAST_CHARGE_CURRENT_CFG_REG,

		.min_u  = 0,

		.max_u  = 2000000,

		.step_u = 100000,

	},

	.fv			= {

		.name   = "float voltage",

		.reg    = CHGR_FLOAT_VOLTAGE_CFG_REG,

		.min_u  = 3600000,

		.max_u  = 4600000,

		.step_u = 20000,

	},

	.usb_icl		= {

		.name   = "usb input current limit",

		.reg    = USBIN_CURRENT_LIMIT_CFG_REG,

		.min_u  = 0,

		.max_u  = 2000000,

		.step_u = 100000,

	},

	.icl_max_stat		= {

		.name   = "dcdc icl max status",

		.reg    = ICL_MAX_STATUS_REG,

		.min_u  = 0,

		.max_u  = 2000000,

		.step_u = 100000,

	},

	.icl_stat		= {

		.name   = "input current limit status",

		.reg    = ICL_STATUS_REG,

		.min_u  = 0,

		.max_u  = 2000000,

		.step_u = 100000,

	},

	.aicl_5v_threshold		= {

		.name   = "AICL 5V threshold",

		.reg    = USBIN_LV_AICL_THRESHOLD_REG,

		.min_u  = 4200,

		.max_u  = 4800,

		.step_u = 200,

	},

};



static struct smb_params smblite_pm5100_params = {

	.fcc			= {

		.name   = "fast charge current",

		.min_u  = 0,

		.max_u  = 1950000,

		.get_proc = smblite_lib_get_fcc,

		.set_proc = smblite_lib_set_fcc,

	},

	.fv			= {

		.name   = "float voltage",

		.min_u  = 3600000,

		.max_u  = 4790000,

		.step_u = 10000,

	},

	.usb_icl		= {

		.name   = "usb input current limit",

		.min_u  = 0,

		.max_u  = 1950000,

		.step_u = 100000,

	},

	.icl_max_stat		= {

		.name   = "dcdc icl max status",

		.min_u  = 0,

		.max_u  = 1950000,

		.step_u = 100000,

	},

	.icl_stat		= {

		.name   = "input current limit status",

		.min_u  = 0,

		.max_u  = 1950000,

		.step_u = 100000,

	},

	.aicl_5v_threshold		= {

		.name   = "AICL 5V threshold",

		.min_u  = 4200,

		.max_u  = 5100,

		.step_u = 300,

	},

};



struct smb_dt_props {

	int			usb_icl_ua;

	int			chg_inhibit_thr_mv;
@@ -137,22 +190,37 @@ static int smblite_chg_config_init(struct smblite *chip) 
	switch (subtype) {

	case PM2250:

		chg->wa_flags |= WEAK_ADAPTER_WA;

		break;

	default:

		pr_err("Unsupported PMIC subtype=%d\n", subtype);

		return -EINVAL;

	}

		chg->base = smb_base[PM2250];

		chg->param = smblite_pm2250_params;

		chg->name = "PM2250_charger";



	rc = smblite_lib_read(chg, DCDC_LDO_CFG_REG, &val);

		rc = smblite_lib_read(chg, DCDC_LDO_CFG_REG(chg->base), &val);

		if (rc < 0) {

			pr_err("Couldn't read LDO config reg rc=%d\n", rc);

			return rc;

		}



		chg->ldo_mode = !!(val & LDO_MODE_BIT);



		break;

	case PM5100:

		chg->base = smb_base[PM5100];

		chg->param = smblite_pm5100_params;

		chg->name = "PM5100_charger";

		break;

	default:

		pr_err("Unsupported PMIC subtype=%d\n", subtype);

		return -EINVAL;

	}



	/* Assign reg to smb params */

	chg->param.fcc.reg = CHGR_FAST_CHARGE_CURRENT_CFG_REG(chg->base);

	chg->param.fv.reg = CHGR_FLOAT_VOLTAGE_CFG_REG(chg->base);

	chg->param.usb_icl.reg = USBIN_CURRENT_LIMIT_CFG_REG(chg->base);

	chg->param.icl_max_stat.reg = ICL_MAX_STATUS_REG(chg->base);

	chg->param.icl_stat.reg = ICL_STATUS_REG(chg->base);

	chg->param.aicl_5v_threshold.reg = USBIN_LV_AICL_THRESHOLD_REG(chg->base);

	chip->chg.chg_param.smb_version = 0;

	chg->param = smblite_params;

	chg->name = "PM2250_charger";



	return rc;

}
@@ -354,7 +422,6 @@ static enum power_supply_property smblite_usb_props[] = { 
	POWER_SUPPLY_PROP_PRESENT,

	POWER_SUPPLY_PROP_ONLINE,

	POWER_SUPPLY_PROP_VOLTAGE_NOW,

	POWER_SUPPLY_PROP_TYPE,

	POWER_SUPPLY_PROP_SCOPE,

	POWER_SUPPLY_PROP_CURRENT_MAX,

	POWER_SUPPLY_PROP_VOLTAGE_MAX,
@@ -387,9 +454,6 @@ static int smblite_usb_get_prop(struct power_supply *psy, 
	case POWER_SUPPLY_PROP_VOLTAGE_NOW:

		rc = smblite_lib_get_prop_usb_voltage_now(chg, val);

		break;

	case POWER_SUPPLY_PROP_TYPE:

		val->intval = POWER_SUPPLY_TYPE_USB;

		break;

	case POWER_SUPPLY_PROP_SCOPE:

		rc = smblite_lib_get_prop_scope(chg, val);

		break;
@@ -397,7 +461,8 @@ static int smblite_usb_get_prop(struct power_supply *psy, 
		val->intval = get_effective_result_locked(chg->usb_icl_votable);

		break;

	case POWER_SUPPLY_PROP_VOLTAGE_MAX:

		val->intval = 5000000;

		val->intval = (chg->hvdcp3_detected) ?

					PM5100_HVDCP3_MAX_VOLTAGE_UV : 5000000;

		break;

	case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMIT:

		/* USB uses this to set SDP current */
@@ -714,7 +779,7 @@ static int smblite_configure_typec(struct smb_charger *chg) 
	int rc;

	u8 val = 0;



	rc = smblite_lib_read(chg, LEGACY_CABLE_STATUS_REG, &val);

	rc = smblite_lib_read(chg, LEGACY_CABLE_STATUS_REG(chg->base), &val);

	if (rc < 0) {

		dev_err(chg->dev, "Couldn't read Legacy status rc=%d\n", rc);

		return rc;
@@ -745,21 +810,21 @@ static int smblite_configure_typec(struct smb_charger *chg) 
	}



	/* Use simple write to clear interrupts */

	rc = smblite_lib_write(chg, TYPE_C_INTERRUPT_EN_CFG_1_REG, 0);

	rc = smblite_lib_write(chg, TYPE_C_INTERRUPT_EN_CFG_1_REG(chg->base), 0);

	if (rc < 0) {

		dev_err(chg->dev,

			"Couldn't configure Type-C interrupts rc=%d\n", rc);

		return rc;

	}



	rc = smblite_lib_write(chg, TYPE_C_INTERRUPT_EN_CFG_2_REG, 0);

	rc = smblite_lib_write(chg, TYPE_C_INTERRUPT_EN_CFG_2_REG(chg->base), 0);

	if (rc < 0) {

		dev_err(chg->dev,

			"Couldn't configure Type-C interrupts rc=%d\n", rc);

		return rc;

	}



	rc = smblite_lib_masked_write(chg, TYPE_C_MODE_CFG_REG,

	rc = smblite_lib_masked_write(chg, TYPE_C_MODE_CFG_REG(chg->base),

					EN_TRY_SNK_BIT | EN_SNK_ONLY_BIT,

					EN_TRY_SNK_BIT);

	if (rc < 0) {
@@ -769,7 +834,7 @@ static int smblite_configure_typec(struct smb_charger *chg) 
		return rc;

	}



	rc = smblite_lib_masked_write(chg, TYPE_C_EXIT_STATE_CFG_REG,

	rc = smblite_lib_masked_write(chg, TYPE_C_EXIT_STATE_CFG_REG(chg->base),

				SEL_SRC_UPPER_REF_BIT, SEL_SRC_UPPER_REF_BIT);

	if (rc < 0)

		dev_err(chg->dev,
@@ -810,7 +875,7 @@ static int smblite_configure_iterm_thresholds_adc(struct smblite *chip) 
		buf = (u8 *)&raw_hi_thresh;

		raw_hi_thresh = buf[1] | (buf[0] << 8);



		rc = smblite_lib_batch_write(chg, CHGR_ADC_ITERM_UP_THD_MSB_REG,

		rc = smblite_lib_batch_write(chg, CHGR_ADC_ITERM_UP_THD_MSB_REG(chg->base),

				(u8 *)&raw_hi_thresh, 2);

		if (rc < 0) {

			dev_err(chg->dev, "Couldn't configure ITERM threshold HIGH rc=%d\n",
@@ -826,7 +891,7 @@ static int smblite_configure_iterm_thresholds_adc(struct smblite *chip) 
		buf = (u8 *)&raw_lo_thresh;

		raw_lo_thresh = buf[1] | (buf[0] << 8);



		rc = smblite_lib_batch_write(chg, CHGR_ADC_ITERM_LO_THD_MSB_REG,

		rc = smblite_lib_batch_write(chg, CHGR_ADC_ITERM_LO_THD_MSB_REG(chg->base),

				(u8 *)&raw_lo_thresh, 2);

		if (rc < 0) {

			dev_err(chg->dev, "Couldn't configure ITERM threshold LOW rc=%d\n",
@@ -859,7 +924,7 @@ static int smblite_configure_recharging(struct smblite *chip) 
	struct smb_charger *chg = &chip->chg;



	/* Configure VBATT-based or automatic recharging */

	rc = smblite_lib_masked_write(chg, CHGR_RECHG_CFG_REG, RECHG_MASK,

	rc = smblite_lib_masked_write(chg, CHGR_RECHG_CFG_REG(chg->base), RECHG_MASK,

				(chip->dt.auto_recharge_vbat_mv > 0) ?

				VBAT_BASED_RECHG_BIT : 0);

	if (rc < 0) {
@@ -874,14 +939,14 @@ static int smblite_configure_recharging(struct smblite *chip) 


		temp = ((temp & 0xFF00) >> 8) | ((temp & 0xFF) << 8);

		rc = smblite_lib_batch_write(chg,

			CHGR_ADC_RECHARGE_THRESHOLD_MSB_REG, (u8 *)&temp, 2);

			CHGR_ADC_RECHARGE_THRESHOLD_MSB_REG(chg->base), (u8 *)&temp, 2);

		if (rc < 0) {

			dev_err(chg->dev, "Couldn't configure ADC_RECHARGE_THRESHOLD REG rc=%d\n",

				rc);

			return rc;

		}

		/* Program the sample count for VBAT based recharge to 3 */

		rc = smblite_lib_masked_write(chg, CHGR_RECHG_CFG_REG,

		rc = smblite_lib_masked_write(chg, CHGR_RECHG_CFG_REG(chg->base),

					NO_OF_SAMPLE_FOR_RCHG, 3);

		if (rc < 0) {

			dev_err(chg->dev, "Couldn't configure CHGR_NO_SAMPLE_FOR_TERM_RCHG_CFG rc=%d\n",
@@ -890,7 +955,7 @@ static int smblite_configure_recharging(struct smblite *chip) 
		}

	}



	rc = smblite_lib_masked_write(chg, CHGR_RECHG_CFG_REG, RECHG_MASK,

	rc = smblite_lib_masked_write(chg, CHGR_RECHG_CFG_REG(chg->base), RECHG_MASK,

				(chip->dt.auto_recharge_soc != -EINVAL) ?

				SOC_BASED_RECHG_BIT : VBAT_BASED_RECHG_BIT);

	if (rc < 0) {
@@ -918,7 +983,7 @@ static int smblite_init_connector_type(struct smb_charger *chg) 
	int rc, type = 0;

	u8 val = 0;



	rc = smblite_lib_read(chg, TYPEC_U_USB_CFG_REG, &val);

	rc = smblite_lib_read(chg, TYPEC_U_USB_CFG_REG(chg->base), &val);

	if (rc < 0) {

		dev_err(chg->dev, "Couldn't read U_USB config rc=%d\n",

				rc);
@@ -931,6 +996,8 @@ static int smblite_init_connector_type(struct smb_charger *chg) 


	if (type) {

		chg->connector_type = QTI_POWER_SUPPLY_CONNECTOR_MICRO_USB;

		/* For micro USB connector, use extcon by default */

		chg->use_extcon = true;

	} else {

		chg->connector_type = QTI_POWER_SUPPLY_CONNECTOR_TYPEC;

		rc = smblite_configure_typec(chg);
@@ -1039,7 +1106,7 @@ static int smblite_init_hw(struct smblite *chip) 


	mask = USBIN_AICL_PERIODIC_RERUN_EN_BIT | USBIN_AICL_RERUN_TIME_MASK;

	val = USBIN_AICL_PERIODIC_RERUN_EN_BIT | AICL_RERUN_TIME_12S_VAL;

	rc = smblite_lib_masked_write(chg, MISC_AICL_RERUN_CFG_REG, mask, val);

	rc = smblite_lib_masked_write(chg, MISC_AICL_RERUN_CFG_REG(chg->base), mask, val);

	if (rc < 0) {

		dev_err(chg->dev, "Couldn't config AICL rerun rc=%d\n", rc);

		return rc;
@@ -1047,7 +1114,7 @@ static int smblite_init_hw(struct smblite *chip) 


	mask = USBIN_AICL_EN_BIT | USBIN_AICL_START_AT_MAX;

	val = USBIN_AICL_EN_BIT;

	rc = smblite_lib_masked_write(chg, USBIN_AICL_OPTIONS_CFG_REG, mask,

	rc = smblite_lib_masked_write(chg, USBIN_AICL_OPTIONS_CFG_REG(chg->base), mask,

				val);

	if (rc < 0) {

		dev_err(chg->dev, "Couldn't config AICL rc=%d\n", rc);
@@ -1055,7 +1122,7 @@ static int smblite_init_hw(struct smblite *chip) 
	}



	if (!chip->dt.disable_suspend_on_collapse) {

		rc = smblite_lib_masked_write(chg, USBIN_INPUT_SUSPEND_REG,

		rc = smblite_lib_masked_write(chg, USBIN_INPUT_SUSPEND_REG(chg->base),

				SUSPEND_ON_COLLAPSE_USBIN_BIT,

				SUSPEND_ON_COLLAPSE_USBIN_BIT);

		if (rc < 0) {
@@ -1072,7 +1139,7 @@ static int smblite_init_hw(struct smblite *chip) 
	}



	/* configure VBUS for software control */

	rc = smblite_lib_masked_write(chg, DCDC_OTG_CFG_REG,

	rc = smblite_lib_masked_write(chg, DCDC_OTG_CFG_REG(chg->base),

				OTG_EN_SRC_CFG_BIT, 0);

	if (rc < 0) {

		dev_err(chg->dev,
@@ -1084,7 +1151,7 @@ static int smblite_init_hw(struct smblite *chip) 
						& BARK_WDOG_TIMEOUT_MASK;

	val |= BITE_WDOG_TIMEOUT_8S << BITE_WDOG_TIMEOUT_SHIFT;



	rc = smblite_lib_masked_write(chg, SNARL_BARK_BITE_WD_CFG_REG,

	rc = smblite_lib_masked_write(chg, SNARL_BARK_BITE_WD_CFG_REG(chg->base),

			BARK_WDOG_TIMEOUT_MASK | BITE_WDOG_TIMEOUT_MASK,

			val);

	if (rc < 0) {
@@ -1097,7 +1164,7 @@ static int smblite_init_hw(struct smblite *chip) 
		| BITE_WDOG_DISABLE_CHARGING_CFG_BIT | WDOG_TIMER_EN_BIT;

	val = WDOG_TIMER_EN_ON_PLUGIN_BIT | BARK_WDOG_INT_EN_BIT

		| BITE_WDOG_DISABLE_CHARGING_CFG_BIT;

	rc = smblite_lib_masked_write(chg, WD_CFG_REG, mask, val);

	rc = smblite_lib_masked_write(chg, WD_CFG_REG(chg->base), mask, val);

	if (rc < 0) {

		pr_err("Couldn't configue WD config rc=%d\n", rc);

		return rc;
@@ -1115,13 +1182,13 @@ static int smblite_init_hw(struct smblite *chip) 
		temp = VBAT_TO_VRAW_ADC(chip->dt.chg_inhibit_thr_mv);

		temp = ((temp & 0xFF00) >> 8) | ((temp & 0xFF) << 8);

		rc = smblite_lib_batch_write(chg,

			CHGR_INHIBIT_THRESHOLD_CFG_REG, (u8 *)&temp, 2);

			CHGR_INHIBIT_THRESHOLD_CFG_REG(chg->base), (u8 *)&temp, 2);

		if (rc < 0) {

			dev_err(chg->dev, "Couldn't configure ADC_RECHARGE_THRESHOLD REG rc=%d\n",

				rc);

			return rc;

		}

		rc = smblite_lib_masked_write(chg, CHGR_INHIBIT_REG,

		rc = smblite_lib_masked_write(chg, CHGR_INHIBIT_REG(chg->base),

					CHGR_INHIBIT_BIT, CHGR_INHIBIT_BIT);

		if (rc < 0) {

			dev_err(chg->dev, "Couldn't enable INHIBIT rc=%d\n",
@@ -1129,7 +1196,7 @@ static int smblite_init_hw(struct smblite *chip) 
			return rc;

		}

	} else {

		rc = smblite_lib_masked_write(chg, CHGR_INHIBIT_REG,

		rc = smblite_lib_masked_write(chg, CHGR_INHIBIT_REG(chg->base),

					CHGR_INHIBIT_BIT, 0);

		if (rc < 0) {

			dev_err(chg->dev, "Couldn't enable INHIBIT rc=%d\n",
@@ -1142,7 +1209,7 @@ static int smblite_init_hw(struct smblite *chip) 
	val = FAST_CHARGE_SAFETY_TIMER_EN_BIT

					| FAST_CHARGE_SAFETY_TIMER_768_MIN;

	rc = smblite_lib_masked_write(chg,

			CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG, mask, val);

			CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG(chg->base), mask, val);

	if (rc < 0) {

		dev_err(chg->dev, "Couldn't set CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG rc=%d\n",

			rc);
@@ -1210,6 +1277,7 @@ static int smblite_determine_initial_status(struct smblite *chip) 
	smblite_batt_temp_changed_irq_handler(0, &irq_data);

	smblite_wdog_bark_irq_handler(0, &irq_data);

	smblite_typec_or_rid_detection_change_irq_handler(0, &irq_data);

	smblite_usb_source_change_irq_handler(0, &irq_data);



	if (chg->usb_id_gpio > 0 &&

		chg->connector_type == QTI_POWER_SUPPLY_CONNECTOR_MICRO_USB)
@@ -1300,6 +1368,11 @@ static struct smb_irq_info smblite_irqs[] = { 
	[USBIN_GT_VT_IRQ] = {

		.name		= "usbin-gtvt",

	},

	[USBIN_SRC_CHANGE_IRQ] = {

		.name		= "usbin-src-change",

		.handler	= smblite_usb_source_change_irq_handler,

		.wake		= true,

	},

	[USBIN_ICL_CHANGE_IRQ] = {

		.name		= "usbin-icl-change",

		.handler	= smblite_icl_change_irq_handler,
@@ -1764,6 +1837,8 @@ static int smblite_probe(struct platform_device *pdev) 
	struct iio_dev *indio_dev;

	struct smb_charger *chg;

	int rc = 0;

	union power_supply_propval pval = {0, };

	const struct apsd_result *apsd;



	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*chip));

	if (!indio_dev)
@@ -1891,6 +1966,14 @@ static int smblite_probe(struct platform_device *pdev) 


	device_init_wakeup(chg->dev, true);



	rc = smblite_lib_get_prop_usb_present(chg, &pval);

	if (rc < 0)

		pr_err("Couldn't read usb present rc=%d\n", rc);



	apsd = smblite_lib_get_apsd_result(chg);



	pr_info("%s charger probed successfully, charger_present=%d, type=%s\n",

			chg->name, pval.intval, apsd->name);

	return rc;



disable_irq:
@@ -1925,7 +2008,7 @@ static void smblite_shutdown(struct platform_device *pdev) 


	/* configure power role for UFP */

	if (chg->connector_type == QTI_POWER_SUPPLY_CONNECTOR_TYPEC)

		smblite_lib_masked_write(chg, TYPE_C_MODE_CFG_REG,

		smblite_lib_masked_write(chg, TYPE_C_MODE_CFG_REG(chg->base),

				TYPEC_POWER_ROLE_CMD_MASK, EN_SNK_ONLY_BIT);

}

drivers/power/supply/qcom/smblite-lib.c

+498 −101

File changed.

Preview size limit exceeded, changes collapsed.

drivers/power/supply/qcom/smblite-lib.h

+35 −0
Original line number Diff line number Diff line
@@ -73,6 +73,11 @@ enum print_reason { 
#define TYPEC_MEDIUM_CURRENT_UA		1500000

#define TYPEC_HIGH_CURRENT_UA		3000000

#define ROLE_REVERSAL_DELAY_MS		500

/* Max supported voltage 6V */

#define HVDCP3_STEP_SIZE_UV		200000

#define PM5100_MAX_HVDCP3_PULSES	5

#define PM5100_HVDCP3_MAX_VOLTAGE_UV	(PM5100_MAX_HVDCP3_PULSES * \

						HVDCP3_STEP_SIZE_UV)



enum smb_mode {

	PARALLEL_MASTER = 0,
@@ -128,6 +133,7 @@ enum smb_irq_index { 
	USBIN_UV_IRQ,

	USBIN_OV_IRQ,

	USBIN_GT_VT_IRQ,

	USBIN_SRC_CHANGE_IRQ,

	USBIN_ICL_CHANGE_IRQ,

	/* TYPEC */

	TYPEC_OR_RID_DETECTION_CHANGE_IRQ,
@@ -156,6 +162,12 @@ enum smb_irq_index { 
	SMB_IRQ_MAX,

};



struct apsd_result {

	const char * const name;

	const u8 bit;

	const int val;

};



enum chg_term_config_src {

	ITERM_SRC_UNSPECIFIED,

	ITERM_SRC_ADC,
@@ -229,6 +241,16 @@ struct smb_iio { 


enum pmic_type {

	PM2250,

	PM5100,

};



struct smb_base_address {

	u16 chg_base;

	u16 batif_base;

	u16 usbin_base;

	u16 misc_base;

	u16 dcdc_base;

	u16 typec_base;

};



struct smb_charger {
@@ -237,6 +259,7 @@ struct smb_charger { 
	struct regmap		*regmap;

	struct smb_irq_info	*irq_info;

	struct smb_params	param;

	struct smb_base_address	base;

	struct smb_iio		iio;

	struct iio_channel	*iio_chans;

	struct iio_channel	**iio_chan_list_qg;
@@ -247,6 +270,7 @@ struct smb_charger { 


	/* locks */

	struct mutex		typec_lock;

	struct mutex		dpdm_lock;



	/* power supplies */

	struct power_supply		*batt_psy;
@@ -256,6 +280,9 @@ struct smb_charger { 
	/* notifiers */

	struct notifier_block	nb;



	/* Regulators */

	struct regulator	*dpdm_reg;



	/* parallel charging */

	struct parallel_params	pl;
@@ -328,6 +355,10 @@ struct smb_charger { 
	int			usb_id_gpio;

	int			usb_id_irq;

	bool			typec_role_swap_failed;

	bool			use_extcon;

	bool			uusb_apsd_rerun_done;

	bool			dpdm_enabled;

	bool			hvdcp3_detected;



	/* workaround flag */

	u32			wa_flags;
@@ -379,6 +410,7 @@ irqreturn_t smblite_typec_or_rid_detection_change_irq_handler(int irq, 
irqreturn_t smblite_temp_change_irq_handler(int irq, void *data);

irqreturn_t smblite_usbin_ov_irq_handler(int irq, void *data);

irqreturn_t smblite_usb_id_irq_handler(int irq, void *data);

irqreturn_t smblite_usb_source_change_irq_handler(int irq, void *data);



int smblite_lib_get_prop_batt_present(struct smb_charger *chg,

				union power_supply_propval *val);
@@ -463,10 +495,13 @@ int smblite_lib_icl_override(struct smb_charger *chg, 
				enum icl_override_mode mode);

int smblite_lib_set_prop_usb_type(struct smb_charger *chg,

				const int val);

const struct apsd_result *smblite_lib_get_apsd_result(struct smb_charger *chg);

void smblite_update_usb_desc(struct smb_charger *chg);

int smblite_lib_init(struct smb_charger *chg);

int smblite_lib_deinit(struct smb_charger *chg);

int smblite_iio_get_prop(struct smb_charger *chg, int channel, int *val);

int smblite_iio_set_prop(struct smb_charger *chg, int channel, int val);

int smblite_lib_get_fcc(struct smb_chg_param *param, u8 val_raw);

int smblite_lib_set_fcc(struct smb_chg_param *param, int val_u, u8 *val_raw);



#endif /* __SMBLITE_LIB_H */

drivers/power/supply/qcom/smblite-reg.h

+93 −67
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2020 The Linux Foundation. All rights reserved.

 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.

 */



#ifndef __SMBLITE_CHARGER_REG_H
@@ -8,13 +8,6 @@ 


#include <linux/bitops.h>



#define CHGR_BASE	0x1000

#define DCDC_BASE	0x1100

#define BATIF_BASE	0x1200

#define USBIN_BASE	0x1300

#define TYPEC_BASE	0X1500

#define MISC_BASE	0x1600



#define PERPH_TYPE_OFFSET	0x04

#define TYPE_MASK		GENMASK(7, 0)

#define PERPH_SUBTYPE_OFFSET	0x05
@@ -24,7 +17,7 @@ 
/********************************

 *  CHGR Peripheral Registers  *

 ********************************/

#define BATTERY_CHARGER_STATUS_1_REG		(CHGR_BASE + 0x06)

#define BATTERY_CHARGER_STATUS_1_REG(base)		(base.chg_base + 0x06)

#define BATTERY_CHARGER_STATUS_MASK		GENMASK(2, 0)

enum {

	INHIBIT_CHARGE = 0,
@@ -37,10 +30,10 @@ enum { 
	DISABLE_CHARGE,

};



#define CHARGER_VBAT_STATUS_REG			(CHGR_BASE + 0x08)

#define CHARGER_VBAT_STATUS_REG(base)			(base.chg_base + 0x08)

#define BAT_OV_BIT				BIT(7)



#define BATTERY_TEMP_STATUS_REG			(BATIF_BASE + 0x0C)

#define BATTERY_TEMP_STATUS_REG(base)			(base.batif_base + 0x0C)

#define BAT_TEMP_STATUS_TOO_HOT_AFP_BIT		BIT(5)

#define BAT_TEMP_STATUS_TOO_HOT_BIT		BIT(4)

#define BAT_TEMP_STATUS_HOT_SOFT_BIT		BIT(3)
@@ -48,37 +41,37 @@ enum { 
#define BAT_TEMP_STATUS_TOO_COLD_BIT		BIT(1)

#define BAT_TEMP_STATUS_TOO_COLD_AFP_BIT	BIT(0)



#define CHARGING_ENABLE_CMD_REG			(CHGR_BASE + 0x46)

#define CHARGING_ENABLE_CMD_REG(base)			(base.chg_base + 0x46)

#define CHARGING_ENABLE_CMD_BIT			BIT(0)

#define CHARGING_PAUSE_CMD_BIT			BIT(4)



#define CHGR_FAST_CHARGE_CURRENT_CFG_REG	(CHGR_BASE + 0x54)

#define CHGR_FLOAT_VOLTAGE_CFG_REG		(CHGR_BASE + 0x58)

#define CHGR_FAST_CHARGE_CURRENT_CFG_REG(base)	(base.chg_base + 0x54)

#define CHGR_FLOAT_VOLTAGE_CFG_REG(base)		(base.chg_base + 0x58)



#define CHGR_TERM_CFG_REG			(CHGR_BASE + 0x60)

#define CHGR_TERM_CFG_REG(base)			(base.chg_base + 0x60)

#define CHGR_ITERM_USE_ANALOG_BIT		BIT(3)



#define CHGR_ADC_ITERM_UP_THD_MSB_REG		(CHGR_BASE + 0x64)

#define CHGR_ADC_ITERM_UP_THD_LSB_REG		(CHGR_BASE + 0x65)

#define CHGR_ADC_ITERM_LO_THD_MSB_REG		(CHGR_BASE + 0x66)

#define CHGR_ADC_ITERM_LO_THD_LSB_REG		(CHGR_BASE + 0x67)

#define CHGR_ADC_ITERM_UP_THD_MSB_REG(base)		(base.chg_base + 0x64)

#define CHGR_ADC_ITERM_UP_THD_LSB_REG(base)		(base.chg_base + 0x65)

#define CHGR_ADC_ITERM_LO_THD_MSB_REG(base)		(base.chg_base + 0x66)

#define CHGR_ADC_ITERM_LO_THD_LSB_REG(base)		(base.chg_base + 0x67)



#define CHGR_RECHG_CFG_REG			(CHGR_BASE + 0x70)

#define CHGR_RECHG_CFG_REG(base)			(base.chg_base + 0x70)

#define RECHG_MASK				GENMASK(7, 6)

#define VBAT_BASED_RECHG_BIT			BIT(7)

#define SOC_BASED_RECHG_BIT			GENMASK(7, 6)

#define NO_OF_SAMPLE_FOR_RCHG			GENMASK(1, 0)



#define CHGR_ADC_RECHARGE_THRESHOLD_MSB_REG	(CHGR_BASE + 0x72)

#define CHGR_ADC_RECHARGE_THRESHOLD_MSB_REG(base)	(base.chg_base + 0x72)



#define CHARGE_RCHG_SOC_THRESHOLD_CFG_REG	(CHGR_BASE + 0x74)

#define CHARGE_RCHG_SOC_THRESHOLD_CFG_REG(base)	(base.chg_base + 0x74)



#define CHGR_INHIBIT_REG			(CHGR_BASE + 0x78)

#define CHGR_INHIBIT_REG(base)			(base.chg_base + 0x78)

#define CHGR_INHIBIT_BIT			BIT(7)



#define CHGR_INHIBIT_THRESHOLD_CFG_REG		(CHGR_BASE + 0x7A)

#define CHGR_INHIBIT_THRESHOLD_CFG_REG(base)		(base.chg_base + 0x7A)



#define CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG	(CHGR_BASE + 0x90)

#define CHGR_FAST_CHARGE_SAFETY_TIMER_CFG_REG(base)	(base.chg_base + 0x90)

#define FAST_CHARGE_SAFETY_TIMER_EN_BIT		BIT(3)

#define FAST_CHARGE_SAFETY_TIMER_MASK		GENMASK(1, 0)

#define FAST_CHARGE_SAFETY_TIMER_192_MIN	0x0
@@ -89,25 +82,25 @@ enum { 
/********************************

 *  DCDC Peripheral Registers  *

 ********************************/

#define ICL_MAX_STATUS_REG			(DCDC_BASE + 0x06)

#define ICL_STATUS_REG				(DCDC_BASE + 0x09)

#define ICL_MAX_STATUS_REG(base)			(base.dcdc_base + 0x06)

#define ICL_STATUS_REG(base)				(base.dcdc_base + 0x09)



#define POWER_PATH_STATUS_REG			(DCDC_BASE + 0x0B)

#define POWER_PATH_STATUS_REG(base)			(base.dcdc_base + 0x0B)

#define VALID_INPUT_POWER_SOURCE_STS_BIT	BIT(7)

#define USE_USBIN_BIT				BIT(5)

#define USBIN_SUSPEND_STS_BIT			BIT(3)

#define POWER_PATH_MASK				GENMASK(1, 0)



#define DCDC_CMD_OTG_REG			(DCDC_BASE + 0x50)

#define DCDC_CMD_OTG_REG(base)			(base.dcdc_base + 0x50)

#define OTG_EN_BIT				BIT(0)



#define DCDC_BST_VREG_SEL			(DCDC_BASE + 0x52)

#define DCDC_BST_VREG_SEL(base)			(base.dcdc_base + 0x52)

#define VBOOST_MASK				GENMASK(1, 0)



#define DCDC_OTG_CFG_REG			(DCDC_BASE + 0x56)

#define DCDC_OTG_CFG_REG(base)			(base.dcdc_base + 0x56)

#define OTG_EN_SRC_CFG_BIT			BIT(0)



#define DCDC_LDO_CFG_REG			(DCDC_BASE + 0x70)

#define DCDC_LDO_CFG_REG(base)			(base.dcdc_base + 0x70)

#define LDO_MODE_BIT				BIT(0)



/********************************
@@ -120,13 +113,13 @@ enum { 
#define BAT_THERM_OR_ID_MISSING_RT_STS_BIT      BIT(1)

#define BAT_TEMP_RT_STS_BIT			BIT(0)



#define SHIP_MODE_REG				(BATIF_BASE + 0x52)

#define SHIP_MODE_REG(base)				(base.batif_base + 0x52)

#define SHIP_MODE_EN_BIT			BIT(0)



#define CHGR_JEITA_HOT_THRESHOLD_REG		(BATIF_BASE + 0x84)

#define CHGR_JEITA_WARM_THRESHOLD_REG		(BATIF_BASE + 0x86)

#define CHGR_JEITA_COOL_THRESHOLD_REG		(BATIF_BASE + 0x88)

#define CHGR_JEITA_COLD_THRESHOLD_REG		(BATIF_BASE + 0x8A)

#define CHGR_JEITA_HOT_THRESHOLD_REG(base)		(base.batif_base + 0x84)

#define CHGR_JEITA_WARM_THRESHOLD_REG(base)		(base.batif_base + 0x86)

#define CHGR_JEITA_COOL_THRESHOLD_REG(base)		(base.batif_base + 0x88)

#define CHGR_JEITA_COLD_THRESHOLD_REG(base)		(base.batif_base + 0x8A)





/********************************
@@ -141,34 +134,67 @@ enum { 
#define USBIN_COLLAPSE_RT_STS_BIT		BIT(1)

#define USBIN_PLUGIN_RT_STS_BIT			BIT(0)



#define USBIN_ICL_OPTIONS_REG			(USBIN_BASE + 0x50)

#define USBIN_ICL_OPTIONS_REG(base)			(base.usbin_base + 0x50)

#define USBIN_MODE_CHG_BIT			BIT(2)

#define USB51_MODE_BIT				BIT(1)

#define CFG_USB3P0_SEL_BIT			BIT(0)



#define CMD_ICL_OVERRIDE_REG			(USBIN_BASE + 0x51)

#define CMD_ICL_OVERRIDE_REG(base)			(base.usbin_base + 0x51)

#define ICL_OVERRIDE_BIT			BIT(0)



#define USBIN_CURRENT_LIMIT_CFG_REG		(USBIN_BASE + 0x52)

#define USBIN_CURRENT_LIMIT_CFG_REG(base)		(base.usbin_base + 0x52)



#define USBIN_INPUT_SUSPEND_REG			(USBIN_BASE + 0x54)

#define USBIN_INPUT_SUSPEND_REG(base)			(base.usbin_base + 0x54)

#define SUSPEND_ON_COLLAPSE_USBIN_BIT		BIT(7)

#define USBIN_SUSPEND_BIT			BIT(0)



#define USBIN_AICL_OPTIONS_CFG_REG		(USBIN_BASE + 0x60)

#define USBIN_AICL_OPTIONS_CFG_REG(base)		(base.usbin_base + 0x60)

#define USBIN_AICL_EN_BIT			BIT(7)

#define USBIN_AICL_START_AT_MAX			BIT(4)

#define USBIN_AICL_STEP_TIMING_SEL_MASK		GENMASK(3, 2)

#define USBIN_IN_COLLAPSE_GF_SEL_MASK		GENMASK(1, 0)



#define USBIN_LV_AICL_THRESHOLD_REG		(USBIN_BASE + 0x63)

#define USBIN_LV_AICL_THRESHOLD_REG(base)		(base.usbin_base + 0x63)



#define USB_CMD_PULLDOWN_REG			(USBIN_BASE + 0x70)

#define USB_CMD_PULLDOWN_REG(base)			(base.usbin_base + 0x70)

#define EN_PULLDOWN_USB_IN_BIT			BIT(0)



#define APSD_STATUS_REG(base)				(base.usbin_base + 0x0a)

#define HVDCP_CHECK_TIMEOUT_BIT			BIT(6)

#define SLOW_PLUGIN_TIMEOUT_BIT			BIT(5)

#define ENUMERATION_DONE_BIT			BIT(4)

#define VADP_CHANGE_DONE_AFTER_AUTH_BIT		BIT(3)

#define QC_AUTH_DONE_STATUS_BIT			BIT(2)

#define QC_CHARGER_BIT				BIT(1)

#define APSD_DTC_STATUS_DONE_BIT		BIT(0)



#define APSD_RESULT_STATUS_REG(base)		(base.usbin_base + 0x0b)

#define APSD_RESULT_STATUS_MASK			GENMASK(6, 0)

#define QC_3P0_BIT				BIT(6)

#define FLOAT_CHARGER_BIT			BIT(4)

#define DCP_CHARGER_BIT				BIT(3)

#define CDP_CHARGER_BIT				BIT(2)

#define OCP_CHARGER_BIT				BIT(1)

#define SDP_CHARGER_BIT				BIT(0)



#define CMD_APSD_REG(base)			(base.usbin_base + 0x45)

#define APSD_RERUN_BIT				BIT(0)



#define USBIN_APSD_EN_REG(base)			(base.usbin_base + 0x44)

#define BC1P2_SRC_DETECT_BIT			BIT(7)



#define CMD_HVDCP_REG(base)			(base.usbin_base + 0x4a)

#define SINGLE_INCREMENT_BIT			BIT(5)

#define SINGLE_DECREMENT_BIT			BIT(4)

#define FORCE_12V_BIT				BIT(3)

#define FORCE_9V_BIT				BIT(2)

#define FORCE_5V_BIT				BIT(1)

#define IDLE_BIT				BIT(0)



/********************************

 *  TYPEC Peripheral Registers  *

 ********************************/

#define TYPE_C_SNK_STATUS_REG			(TYPEC_BASE + 0x06)

#define TYPE_C_SNK_STATUS_REG(base)			(base.typec_base + 0x06)

#define DETECTED_SRC_TYPE_MASK			GENMASK(6, 0)

#define SNK_DAM_500MA_BIT			BIT(6)

#define SNK_DAM_1500MA_BIT			BIT(5)
@@ -178,7 +204,7 @@ enum { 
#define SNK_RP_3P0_BIT				BIT(1)

#define SNK_RP_SHORT_BIT			BIT(0)



#define TYPE_C_SRC_STATUS_REG			(TYPEC_BASE + 0x08)

#define TYPE_C_SRC_STATUS_REG(base)			(base.typec_base + 0x08)

#define DETECTED_SNK_TYPE_MASK			GENMASK(4, 0)

#define SRC_HIGH_BATT_BIT			BIT(5)

#define SRC_DEBUG_ACCESS_BIT			BIT(4)
@@ -186,27 +212,27 @@ enum { 
#define SRC_RA_OPEN_BIT				BIT(1)

#define AUDIO_ACCESS_RA_RA_BIT			BIT(0)



#define TYPE_C_STATE_MACHINE_STATUS_REG		(TYPEC_BASE + 0x09)

#define TYPE_C_STATE_MACHINE_STATUS_REG(base)		(base.typec_base + 0x09)

#define TYPEC_ATTACH_DETACH_STATE_BIT		BIT(5)



#define TYPE_C_MISC_STATUS_REG			(TYPEC_BASE + 0x0B)

#define TYPE_C_MISC_STATUS_REG(base)			(base.typec_base + 0x0B)

#define SNK_SRC_MODE_BIT			BIT(6)

#define TYPEC_VBUS_ERROR_STATUS_BIT		BIT(4)

#define TYPEC_TCCDEBOUNCE_DONE_STATUS_BIT	BIT(3)

#define CC_ORIENTATION_BIT			BIT(1)

#define CC_ATTACHED_BIT				BIT(0)



#define LEGACY_CABLE_STATUS_REG			(TYPEC_BASE + 0x0D)

#define LEGACY_CABLE_STATUS_REG(base)			(base.typec_base + 0x0D)

#define TYPEC_LEGACY_CABLE_STATUS_BIT		BIT(1)

#define TYPEC_NONCOMP_LEGACY_CABLE_STATUS_BIT	BIT(0)



#define TYPEC_U_USB_STATUS_REG			(TYPEC_BASE + 0x0F)

#define TYPEC_U_USB_STATUS_REG(base)			(base.typec_base + 0x0F)

#define U_USB_GROUND_NOVBUS_BIT			BIT(6)

#define U_USB_GROUND_BIT			BIT(4)

#define U_USB_FLOAT1_BIT			BIT(2)

#define U_USB_FLOAT2_BIT			BIT(0)



#define TYPE_C_MODE_CFG_REG			(TYPEC_BASE + 0x44)

#define TYPE_C_MODE_CFG_REG(base)			(base.typec_base + 0x44)

#define TYPEC_TRY_MODE_MASK			GENMASK(4, 3)

#define EN_TRY_SNK_BIT				BIT(4)

#define EN_TRY_SRC_BIT				BIT(3)
@@ -215,15 +241,15 @@ enum { 
#define EN_SNK_ONLY_BIT				BIT(1)

#define TYPEC_DISABLE_CMD_BIT			BIT(0)



#define DEBUG_ACCESS_SRC_CFG_REG		(TYPEC_BASE + 0x4C)

#define DEBUG_ACCESS_SRC_CFG_REG(base)		(base.typec_base + 0x4C)

#define EN_UNORIENTED_DEBUG_ACCESS_SRC_BIT	BIT(0)



#define TYPE_C_EXIT_STATE_CFG_REG		(TYPEC_BASE + 0x50)

#define TYPE_C_EXIT_STATE_CFG_REG(base)		(base.typec_base + 0x50)

#define BYPASS_VSAFE0V_DURING_ROLE_SWAP_BIT	BIT(3)

#define SEL_SRC_UPPER_REF_BIT			BIT(2)

#define EXIT_SNK_BASED_ON_CC_BIT		BIT(0)



#define TYPE_C_CURRSRC_CFG_REG			(TYPEC_BASE + 0x52)

#define TYPE_C_CURRSRC_CFG_REG(base)			(base.typec_base + 0x52)

#define TYPEC_SRC_RP_SEL_MASK			GENMASK(1, 0)

enum {

	TYPEC_SRC_RP_STD,
@@ -233,7 +259,7 @@ enum { 
	TYPEC_SRC_RP_MAX_ELEMENTS

};



#define TYPE_C_INTERRUPT_EN_CFG_1_REG			(TYPEC_BASE + 0x5E)

#define TYPE_C_INTERRUPT_EN_CFG_1_REG(base)		(base.typec_base + 0x5E)

#define TYPEC_LEGACY_CABLE_INT_EN_BIT			BIT(7)

#define TYPEC_NONCOMPLIANT_LEGACY_CABLE_INT_EN_BIT	BIT(6)

#define TYPEC_TRYSOURCE_DETECT_INT_EN_BIT		BIT(5)
@@ -243,7 +269,7 @@ enum { 
#define TYPEC_VBUS_DEASSERT_INT_EN_BIT			BIT(1)

#define TYPEC_VBUS_ASSERT_INT_EN_BIT			BIT(0)



#define TYPE_C_INTERRUPT_EN_CFG_2_REG		(TYPEC_BASE + 0x60)

#define TYPE_C_INTERRUPT_EN_CFG_2_REG(base)		(base.typec_base + 0x60)

#define TYPEC_SRC_BATT_HPWR_INT_EN_BIT		BIT(6)

#define MICRO_USB_STATE_CHANGE_INT_EN_BIT	BIT(5)

#define TYPEC_STATE_MACHINE_CHANGE_INT_EN_BIT	BIT(4)
@@ -252,13 +278,13 @@ enum { 
#define TYPEC_VBUS_ERROR_INT_EN_BIT		BIT(1)

#define TYPEC_DEBOUNCE_DONE_INT_EN_BIT		BIT(0)



#define TYPEC_U_USB_CFG_REG			(TYPEC_BASE + 0x70)

#define TYPEC_U_USB_CFG_REG(base)			(base.typec_base + 0x70)

#define EN_MICRO_USB_MODE_BIT			BIT(0)



/********************************

 *  MISC Peripheral Registers  *

 ********************************/

#define TEMP_RANGE_STATUS_REG			(MISC_BASE + 0x08)

#define TEMP_RANGE_STATUS_REG(base)			(base.misc_base + 0x08)

#define THERM_REG_ACTIVE_BIT			BIT(6)

#define TLIM_BIT				BIT(5)

#define TEMP_RANGE_MASK				GENMASK(4, 1)
@@ -268,37 +294,37 @@ enum { 
#define TEMP_BELOW_RANGE_BIT			BIT(1)

#define THERMREG_DISABLED_BIT			BIT(0)



#define DIE_TEMP_STATUS_REG			(MISC_BASE + 0x09)

#define DIE_TEMP_STATUS_REG(base)			(base.misc_base + 0x09)

#define DIE_TEMP_MASK				GENMASK(3, 0)

#define DIE_TEMP_SHDN_BIT			BIT(3)

#define DIE_TEMP_RST_BIT			BIT(2)

#define DIE_TEMP_UB_BIT				BIT(1)

#define DIE_TEMP_LB_BIT				BIT(0)



#define AICL_STATUS_REG				(MISC_BASE + 0x06)

#define AICL_STATUS_REG(base)				(base.misc_base + 0x06)

#define SOFT_ILIMIT_BIT				BIT(6)

#define AICL_DONE_BIT				BIT(0)



#define AICL_CMD_REG				(MISC_BASE + 0x50)

#define AICL_CMD_REG(base)				(base.misc_base + 0x50)

#define RESTART_AICL_BIT			BIT(1)

#define RERUN_AICL_BIT				BIT(0)



#define MISC_SMB_EN_CMD_REG			(MISC_BASE + 0x4C)

#define MISC_SMB_EN_CMD_REG(base)			(base.misc_base + 0x4C)

#define SMB_EN_OVERRIDE_VALUE_BIT		BIT(0)

#define SMB_EN_OVERRIDE_BIT			BIT(1)



#define MISC_AICL_RERUN_CFG_REG			(MISC_BASE + 0x54)

#define MISC_AICL_RERUN_CFG_REG(base)			(base.misc_base + 0x54)

#define USBIN_AICL_PERIODIC_RERUN_EN_BIT	BIT(5)

#define USBIN_AICL_RERUN_TIME_MASK		GENMASK(1, 0)

#define AICL_RERUN_TIME_12S_VAL			0x01



#define WD_CFG_REG				(MISC_BASE + 0x58)

#define WD_CFG_REG(base)				(base.misc_base + 0x58)

#define BITE_WDOG_DISABLE_CHARGING_CFG_BIT	BIT(7)

#define BARK_WDOG_INT_EN_BIT			BIT(4)

#define WDOG_TIMER_EN_ON_PLUGIN_BIT		BIT(1)

#define WDOG_TIMER_EN_BIT			BIT(0)



#define SNARL_BARK_BITE_WD_CFG_REG		(MISC_BASE + 0x59)

#define SNARL_BARK_BITE_WD_CFG_REG(base)		(base.misc_base + 0x59)

#define SNARL_WDOG_TIMEOUT_MASK                 GENMASK(2, 0)

#define SNARL_WDOG_TMOUT_62P5MS			0x0

#define SNARL_WDOG_TMOUT_1S			0x4
@@ -310,7 +336,7 @@ enum { 
#define BITE_WDOG_TIMEOUT_SHIFT			6

#define MIN_WD_BARK_TIME			16



#define BARK_BITE_WDOG_PET_REG			(MISC_BASE + 0x5A)

#define BARK_BITE_WDOG_PET_REG(base)			(base.misc_base + 0x5A)

#define BARK_BITE_WDOG_PET_BIT			BIT(0)



#endif /* __SMBLITE_CHARGER_REG_H */