Merge "msm: kgsl: Capture gpu globals in hwsched snapshot" (4b9bef81) · Commits · e / devices / android_kernel_fairphone_FP5

drivers/gpu/msm/Makefile

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -44,6 +44,7 @@ msm_kgsl-y += \
	adreno_cp_parser.o \		adreno_cp_parser.o \
	adreno_dispatch.o \		adreno_dispatch.o \
	adreno_drawctxt.o \		adreno_drawctxt.o \
			adreno_hwsched.o \
	adreno_ioctl.o \		adreno_ioctl.o \
	adreno_perfcounter.o \		adreno_perfcounter.o \
	adreno_ringbuffer.o \		adreno_ringbuffer.o \

drivers/gpu/msm/adreno.c

+60 −5

Original line number	Original line	Diff line number	Diff line
	@@ -22,6 +22,7 @@
	#include "adreno_a5xx.h"		#include "adreno_a5xx.h"
	#include "adreno_a6xx.h"		#include "adreno_a6xx.h"
	#include "adreno_compat.h"		#include "adreno_compat.h"
			#include "adreno_hwsched.h"
	#include "adreno_iommu.h"		#include "adreno_iommu.h"
	#include "adreno_trace.h"		#include "adreno_trace.h"
	#include "kgsl_bus.h"		#include "kgsl_bus.h"
	@@ -1522,10 +1523,15 @@ static void adreno_unbind(struct device *dev)

	kgsl_pwrscale_close(device);		kgsl_pwrscale_close(device);

			if (test_bit(GMU_DISPATCH, &device->gmu_core.flags))
			adreno_hwsched_dispatcher_close(adreno_dev);
			else {
	adreno_dispatcher_close(adreno_dev);		adreno_dispatcher_close(adreno_dev);

	adreno_ringbuffer_close(adreno_dev);		adreno_ringbuffer_close(adreno_dev);

	adreno_fault_detect_stop(adreno_dev);		adreno_fault_detect_stop(adreno_dev);
			}

	kfree(adreno_ft_regs);		kfree(adreno_ft_regs);
	adreno_ft_regs = NULL;		adreno_ft_regs = NULL;
	@@ -1875,11 +1881,11 @@ static int adreno_last_close(struct kgsl_device *device)
	* Wait up to 1 second for the active count to go low		* Wait up to 1 second for the active count to go low
	* and then start complaining about it		* and then start complaining about it
	*/		*/
	if (kgsl_active_count_wait(device, 0)) {		if (kgsl_active_count_wait(device, 0, HZ)) {
	dev_err(device->dev,		dev_err(device->dev,
	"Waiting for the active count to become 0\n");		"Waiting for the active count to become 0\n");

	while (kgsl_active_count_wait(device, 0))		while (kgsl_active_count_wait(device, 0, HZ))
	dev_err(device->dev,		dev_err(device->dev,
	"Still waiting for the active count\n");		"Still waiting for the active count\n");
	}		}
	@@ -3195,6 +3201,45 @@ void adreno_cx_misc_regrmw(struct adreno_device *adreno_dev,
	adreno_cx_misc_regwrite(adreno_dev, offsetwords, val \| bits);		adreno_cx_misc_regwrite(adreno_dev, offsetwords, val \| bits);
	}		}

			void adreno_profile_submit_time(struct adreno_submit_time *time)
			{
			struct kgsl_drawobj *drawobj;
			struct kgsl_drawobj_cmd *cmdobj;
			struct kgsl_mem_entry *entry;
			struct kgsl_drawobj_profiling_buffer *profile_buffer;

			drawobj = time->drawobj;
			if (drawobj == NULL)
			return;

			cmdobj = CMDOBJ(drawobj);
			entry = cmdobj->profiling_buf_entry;
			if (!entry)
			return;

			profile_buffer = kgsl_gpuaddr_to_vaddr(&entry->memdesc,
			cmdobj->profiling_buffer_gpuaddr);

			if (profile_buffer == NULL)
			return;

			/* Return kernel clock time to the client if requested */
			if (drawobj->flags & KGSL_DRAWOBJ_PROFILING_KTIME) {
			u64 secs = time->ktime;

			profile_buffer->wall_clock_ns =
			do_div(secs, NSEC_PER_SEC);
			profile_buffer->wall_clock_s = secs;
			} else {
			profile_buffer->wall_clock_s = time->utime.tv_sec;
			profile_buffer->wall_clock_ns = time->utime.tv_nsec;
			}

			profile_buffer->gpu_ticks_queued = time->ticks;

			kgsl_memdesc_unmap(&entry->memdesc);
			}

	/**		/**
	* adreno_waittimestamp - sleep while waiting for the specified timestamp		* adreno_waittimestamp - sleep while waiting for the specified timestamp
	* @device - pointer to a KGSL device structure		* @device - pointer to a KGSL device structure
	@@ -3607,6 +3652,12 @@ static int adreno_queue_cmds(struct kgsl_device_private *dev_priv,
	struct kgsl_context context, struct kgsl_drawobj drawobj[],		struct kgsl_context context, struct kgsl_drawobj drawobj[],
	u32 count, u32 *timestamp)		u32 count, u32 *timestamp)
	{		{
			struct kgsl_device *device = dev_priv->device;

			if (test_bit(GMU_DISPATCH, &device->gmu_core.flags))
			return adreno_hwsched_queue_cmds(dev_priv, context, drawobj,
			count, timestamp);

	return adreno_dispatcher_queue_cmds(dev_priv, context, drawobj, count,		return adreno_dispatcher_queue_cmds(dev_priv, context, drawobj, count,
	timestamp);		timestamp);
	}		}
	@@ -3614,6 +3665,10 @@ static int adreno_queue_cmds(struct kgsl_device_private *dev_priv,
	static void adreno_drawctxt_sched(struct kgsl_device *device,		static void adreno_drawctxt_sched(struct kgsl_device *device,
	struct kgsl_context *context)		struct kgsl_context *context)
	{		{
			if (test_bit(GMU_DISPATCH, &device->gmu_core.flags))
			return adreno_hwsched_queue_context(device,
			ADRENO_CONTEXT(context));

	adreno_dispatcher_queue_context(device, ADRENO_CONTEXT(context));		adreno_dispatcher_queue_context(device, ADRENO_CONTEXT(context));
	}		}

drivers/gpu/msm/adreno.h

+29 −6

Original line number	Original line	Diff line number	Diff line
	@@ -806,7 +806,7 @@ struct adreno_gpudev {
	int (preemption_init)(struct adreno_device adreno_dev);		int (preemption_init)(struct adreno_device adreno_dev);
	void (preemption_schedule)(struct adreno_device adreno_dev);		void (preemption_schedule)(struct adreno_device adreno_dev);
	int (preemption_context_init)(struct kgsl_context context);		int (preemption_context_init)(struct kgsl_context context);
	void (preemption_context_destroy)(struct kgsl_context context);		void (context_detach)(struct adreno_context drawctxt);
	void (clk_set_options)(struct adreno_device adreno_dev,		void (clk_set_options)(struct adreno_device adreno_dev,
	const char name, struct clk clk, bool on);		const char name, struct clk clk, bool on);
	void (pre_reset)(struct adreno_device adreno_dev);		void (pre_reset)(struct adreno_device adreno_dev);
	@@ -1658,13 +1658,9 @@ static inline int adreno_perfcntr_active_oob_get(

	if (!ret) {		if (!ret) {
	ret = gmu_core_dev_oob_set(device, oob_perfcntr);		ret = gmu_core_dev_oob_set(device, oob_perfcntr);
	if (ret) {		if (ret)
	adreno_set_gpu_fault(adreno_dev,
	ADRENO_GMU_FAULT_SKIP_SNAPSHOT);
	adreno_dispatcher_schedule(device);
	adreno_active_count_put(adreno_dev);		adreno_active_count_put(adreno_dev);
	}		}
	}

	return ret;		return ret;
	}		}
	@@ -1777,6 +1773,13 @@ static inline void adreno_reg_offset_init(u32 *reg_offsets)
	}		}
	}		}

			static inline u32 adreno_get_level(u32 priority)
			{
			u32 level = priority / KGSL_PRIORITY_MAX_RB_LEVELS;

			return min_t(u32, level, KGSL_PRIORITY_MAX_RB_LEVELS - 1);
			}

	int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,		int adreno_gmu_fenced_write(struct adreno_device *adreno_dev,
	enum adreno_regs offset, unsigned int val,		enum adreno_regs offset, unsigned int val,
	unsigned int fence_mask);		unsigned int fence_mask);
	@@ -1925,4 +1928,24 @@ void gmu_fault_snapshot(struct kgsl_device *device);
	* Return: 0 on success or negative error on failure		* Return: 0 on success or negative error on failure
	*/		*/
	int adreno_suspend_context(struct kgsl_device *device);		int adreno_suspend_context(struct kgsl_device *device);

			/*
			* adreno_profile_submit_time - Populate profiling buffer with timestamps
			* @time: Container for the statistics
			*
			* Populate the draw object user profiling buffer with the timestamps
			* recored in the adreno_submit_time structure at the time of draw object
			* submission.
			*/
			void adreno_profile_submit_time(struct adreno_submit_time *time);

			/**
			* adreno_mark_guilty_context - Mark the given context as guilty
			* (failed recovery)
			* @device: Pointer to a KGSL device structure
			* @id: Context ID of the guilty context (or 0 to mark all as guilty)
			*
			* Mark the given (or all) context(s) as guilty (failed recovery)
			*/
			void adreno_mark_guilty_context(struct kgsl_device *device, unsigned int id);
	#endif /__ADRENO_H /		#endif /__ADRENO_H /

drivers/gpu/msm/adreno_a6xx.c

+4 −25

Original line number	Original line	Diff line number	Diff line
	@@ -17,22 +17,6 @@
	#include "adreno_trace.h"		#include "adreno_trace.h"
	#include "kgsl_trace.h"		#include "kgsl_trace.h"

	#define A6XX_INT_MASK \
	((1 << A6XX_INT_CP_AHB_ERROR) \| \
	(1 << A6XX_INT_ATB_ASYNCFIFO_OVERFLOW) \| \
	(1 << A6XX_INT_RBBM_GPC_ERROR) \| \
	(1 << A6XX_INT_CP_SW) \| \
	(1 << A6XX_INT_CP_HW_ERROR) \| \
	(1 << A6XX_INT_CP_IB2) \| \
	(1 << A6XX_INT_CP_IB1) \| \
	(1 << A6XX_INT_CP_RB) \| \
	(1 << A6XX_INT_CP_CACHE_FLUSH_TS) \| \
	(1 << A6XX_INT_RBBM_ATB_BUS_OVERFLOW) \| \
	(1 << A6XX_INT_RBBM_HANG_DETECT) \| \
	(1 << A6XX_INT_UCHE_OOB_ACCESS) \| \
	(1 << A6XX_INT_UCHE_TRAP_INTR) \| \
	(1 << A6XX_INT_TSB_WRITE_ERROR))

	/* IFPC & Preemption static powerup restore list */		/* IFPC & Preemption static powerup restore list */
	static u32 a6xx_pwrup_reglist[] = {		static u32 a6xx_pwrup_reglist[] = {
	A6XX_VSC_ADDR_MODE_CNTL,		A6XX_VSC_ADDR_MODE_CNTL,
	@@ -439,8 +423,6 @@ void a6xx_start(struct adreno_device *adreno_dev)
	unsigned int rgb565_predicator = 0;		unsigned int rgb565_predicator = 0;
	static bool patch_reglist;		static bool patch_reglist;

	adreno_dev->irq_mask = A6XX_INT_MASK;

	/* enable hardware clockgating */		/* enable hardware clockgating */
	a6xx_hwcg_set(adreno_dev, true);		a6xx_hwcg_set(adreno_dev, true);

	@@ -2555,6 +2537,8 @@ static int a6xx_probe(struct platform_device *pdev,

	INIT_WORK(&device->idle_check_ws, kgsl_idle_check);		INIT_WORK(&device->idle_check_ws, kgsl_idle_check);

			adreno_dev->irq_mask = A6XX_INT_MASK;

	return 0;		return 0;
	}		}

	@@ -2824,7 +2808,6 @@ struct adreno_gpudev adreno_a6xx_gpudev = {
	.preemption_schedule = a6xx_preemption_schedule,		.preemption_schedule = a6xx_preemption_schedule,
	.set_marker = a6xx_set_marker,		.set_marker = a6xx_set_marker,
	.preemption_context_init = a6xx_preemption_context_init,		.preemption_context_init = a6xx_preemption_context_init,
	.preemption_context_destroy = a6xx_preemption_context_destroy,
	.sptprac_is_on = a6xx_sptprac_is_on,		.sptprac_is_on = a6xx_sptprac_is_on,
	.ccu_invalidate = a6xx_ccu_invalidate,		.ccu_invalidate = a6xx_ccu_invalidate,
	.perfcounter_update = a6xx_perfcounter_update,		.perfcounter_update = a6xx_perfcounter_update,
	@@ -2841,13 +2824,13 @@ struct adreno_gpudev adreno_a6xx_gpudev = {
	struct adreno_gpudev adreno_a6xx_hwsched_gpudev = {		struct adreno_gpudev adreno_a6xx_hwsched_gpudev = {
	.reg_offsets = a6xx_register_offsets,		.reg_offsets = a6xx_register_offsets,
	.probe = a6xx_hwsched_probe,		.probe = a6xx_hwsched_probe,
	.snapshot = a6xx_gmu_snapshot,		.snapshot = a6xx_hwsched_snapshot,
	.irq_handler = a6xx_irq_handler,		.irq_handler = a6xx_irq_handler,
	.perfcounters = &a6xx_perfcounters,		.perfcounters = &a6xx_perfcounters,
	.read_throttling_counters = a6xx_read_throttling_counters,		.read_throttling_counters = a6xx_read_throttling_counters,
	.iommu_fault_block = a6xx_iommu_fault_block,		.iommu_fault_block = a6xx_iommu_fault_block,
	.preemption_context_init = a6xx_preemption_context_init,		.preemption_context_init = a6xx_preemption_context_init,
	.preemption_context_destroy = a6xx_preemption_context_destroy,		.context_detach = a6xx_hwsched_context_detach,
	.perfcounter_update = a6xx_perfcounter_update,		.perfcounter_update = a6xx_perfcounter_update,
	#ifdef CONFIG_QCOM_KGSL_CORESIGHT		#ifdef CONFIG_QCOM_KGSL_CORESIGHT
	.coresight = {&a6xx_coresight, &a6xx_coresight_cx},		.coresight = {&a6xx_coresight, &a6xx_coresight_cx},
	@@ -2879,7 +2862,6 @@ struct adreno_gpudev adreno_a6xx_gmu_gpudev = {
	.preemption_schedule = a6xx_preemption_schedule,		.preemption_schedule = a6xx_preemption_schedule,
	.set_marker = a6xx_set_marker,		.set_marker = a6xx_set_marker,
	.preemption_context_init = a6xx_preemption_context_init,		.preemption_context_init = a6xx_preemption_context_init,
	.preemption_context_destroy = a6xx_preemption_context_destroy,
	.sptprac_is_on = a6xx_sptprac_is_on,		.sptprac_is_on = a6xx_sptprac_is_on,
	.ccu_invalidate = a6xx_ccu_invalidate,		.ccu_invalidate = a6xx_ccu_invalidate,
	.perfcounter_update = a6xx_perfcounter_update,		.perfcounter_update = a6xx_perfcounter_update,
	@@ -2913,7 +2895,6 @@ struct adreno_gpudev adreno_a6xx_rgmu_gpudev = {
	.preemption_schedule = a6xx_preemption_schedule,		.preemption_schedule = a6xx_preemption_schedule,
	.set_marker = a6xx_set_marker,		.set_marker = a6xx_set_marker,
	.preemption_context_init = a6xx_preemption_context_init,		.preemption_context_init = a6xx_preemption_context_init,
	.preemption_context_destroy = a6xx_preemption_context_destroy,
	.sptprac_is_on = a6xx_sptprac_is_on,		.sptprac_is_on = a6xx_sptprac_is_on,
	.ccu_invalidate = a6xx_ccu_invalidate,		.ccu_invalidate = a6xx_ccu_invalidate,
	.perfcounter_update = a6xx_perfcounter_update,		.perfcounter_update = a6xx_perfcounter_update,
	@@ -2947,7 +2928,6 @@ struct adreno_gpudev adreno_a619_holi_gpudev = {
	.preemption_schedule = a6xx_preemption_schedule,		.preemption_schedule = a6xx_preemption_schedule,
	.set_marker = a6xx_set_marker,		.set_marker = a6xx_set_marker,
	.preemption_context_init = a6xx_preemption_context_init,		.preemption_context_init = a6xx_preemption_context_init,
	.preemption_context_destroy = a6xx_preemption_context_destroy,
	.sptprac_is_on = a6xx_sptprac_is_on,		.sptprac_is_on = a6xx_sptprac_is_on,
	.ccu_invalidate = a6xx_ccu_invalidate,		.ccu_invalidate = a6xx_ccu_invalidate,
	.perfcounter_update = a6xx_perfcounter_update,		.perfcounter_update = a6xx_perfcounter_update,
	@@ -2984,7 +2964,6 @@ struct adreno_gpudev adreno_a630_gpudev = {
	.preemption_schedule = a6xx_preemption_schedule,		.preemption_schedule = a6xx_preemption_schedule,
	.set_marker = a6xx_set_marker,		.set_marker = a6xx_set_marker,
	.preemption_context_init = a6xx_preemption_context_init,		.preemption_context_init = a6xx_preemption_context_init,
	.preemption_context_destroy = a6xx_preemption_context_destroy,
	.sptprac_is_on = a6xx_sptprac_is_on,		.sptprac_is_on = a6xx_sptprac_is_on,
	.ccu_invalidate = a6xx_ccu_invalidate,		.ccu_invalidate = a6xx_ccu_invalidate,
	.perfcounter_update = a6xx_perfcounter_update,		.perfcounter_update = a6xx_perfcounter_update,

drivers/gpu/msm/adreno_a6xx.h

+28 −0

Original line number	Original line	Diff line number	Diff line
	@@ -13,6 +13,9 @@
	#include "adreno_a6xx_gmu.h"		#include "adreno_a6xx_gmu.h"
	#include "adreno_a6xx_rgmu.h"		#include "adreno_a6xx_rgmu.h"

			/* Snapshot section size of each CP preemption record for A6XX */
			#define A6XX_SNAPSHOT_CP_CTXRECORD_SIZE_IN_BYTES (64 * 1024)

	extern const struct adreno_power_ops a6xx_gmu_power_ops;		extern const struct adreno_power_ops a6xx_gmu_power_ops;
	extern const struct adreno_power_ops a6xx_rgmu_power_ops;		extern const struct adreno_power_ops a6xx_rgmu_power_ops;
	extern const struct adreno_power_ops a630_gmu_power_ops;		extern const struct adreno_power_ops a630_gmu_power_ops;
	@@ -186,6 +189,31 @@ struct cpu_gpu_lock {
	/* Size of the CP_INIT pm4 stream in dwords */		/* Size of the CP_INIT pm4 stream in dwords */
	#define A6XX_CP_INIT_DWORDS 12		#define A6XX_CP_INIT_DWORDS 12

			#define A6XX_INT_MASK \
			((1 << A6XX_INT_CP_AHB_ERROR) \| \
			(1 << A6XX_INT_ATB_ASYNCFIFO_OVERFLOW) \| \
			(1 << A6XX_INT_RBBM_GPC_ERROR) \| \
			(1 << A6XX_INT_CP_SW) \| \
			(1 << A6XX_INT_CP_HW_ERROR) \| \
			(1 << A6XX_INT_CP_IB2) \| \
			(1 << A6XX_INT_CP_IB1) \| \
			(1 << A6XX_INT_CP_RB) \| \
			(1 << A6XX_INT_CP_CACHE_FLUSH_TS) \| \
			(1 << A6XX_INT_RBBM_ATB_BUS_OVERFLOW) \| \
			(1 << A6XX_INT_RBBM_HANG_DETECT) \| \
			(1 << A6XX_INT_UCHE_OOB_ACCESS) \| \
			(1 << A6XX_INT_UCHE_TRAP_INTR) \| \
			(1 << A6XX_INT_TSB_WRITE_ERROR))

			#define A6XX_HWSCHED_INT_MASK \
			((1 << A6XX_INT_CP_AHB_ERROR) \| \
			(1 << A6XX_INT_ATB_ASYNCFIFO_OVERFLOW) \| \
			(1 << A6XX_INT_RBBM_GPC_ERROR) \| \
			(1 << A6XX_INT_RBBM_ATB_BUS_OVERFLOW) \| \
			(1 << A6XX_INT_UCHE_OOB_ACCESS) \| \
			(1 << A6XX_INT_UCHE_TRAP_INTR) \| \
			(1 << A6XX_INT_TSB_WRITE_ERROR))

	/**		/**
	* to_a6xx_core - return the a6xx specific GPU core struct		* to_a6xx_core - return the a6xx specific GPU core struct
	* @adreno_dev: An Adreno GPU device handle		* @adreno_dev: An Adreno GPU device handle