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Commit 4b3d0da6 authored by Jordan Crouse's avatar Jordan Crouse
Browse files

msm: kgsl: Move a3xx perfcounters to target specific 



Add support for per-group enable and read functions and move all of the
3xx perfcounters to target specific code with specialized functions.
The a3xx functions are the most "non-standard" of the bunch because of
the freeze/unfreeze wrappers we need for most registers.

Change-Id: Ic0dedbad110eeaf667f6f44d809d4cd90942451a
Signed-off-by: default avatarJordan Crouse <jcrouse@codeaurora.org>
parent 6a91a7d5

drivers/gpu/msm/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ msm_kgsl-$(CONFIG_SYNC_FILE) += kgsl_sync.o 
msm_kgsl-y += \

	adreno.o \

	adreno_a3xx.o \

	adreno_a3xx_perfcounter.o \

	adreno_a3xx_snapshot.o \

	adreno_a5xx.o \

	adreno_a5xx_preempt.o \

drivers/gpu/msm/adreno.h

+0 −2
Original line number Diff line number Diff line
@@ -676,7 +676,6 @@ enum adreno_regs { 
	ADRENO_REG_CP_PREEMPT_LEVEL_STATUS,

	ADRENO_REG_RBBM_STATUS,

	ADRENO_REG_RBBM_STATUS3,

	ADRENO_REG_RBBM_PERFCTR_CTL,

	ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0,

	ADRENO_REG_RBBM_PERFCTR_LOAD_CMD1,

	ADRENO_REG_RBBM_PERFCTR_LOAD_CMD2,
@@ -691,7 +690,6 @@ enum adreno_regs { 
	ADRENO_REG_SQ_GPR_MANAGEMENT,

	ADRENO_REG_SQ_INST_STORE_MANAGEMENT,

	ADRENO_REG_TP0_CHICKEN,

	ADRENO_REG_RBBM_RBBM_CTL,

	ADRENO_REG_UCHE_INVALIDATE0,

	ADRENO_REG_UCHE_INVALIDATE1,

	ADRENO_REG_RBBM_PERFCTR_RBBM_0_LO,

drivers/gpu/msm/adreno_a3xx.c

+1 −211
Original line number Diff line number Diff line
@@ -826,214 +826,6 @@ static struct adreno_irq_funcs a3xx_irq_funcs[32] = { 
	ADRENO_IRQ_CALLBACK(a3xx_err_callback),  /* 25 - UCHE_OOB_ACCESS */

};



/*

 * Define the available perfcounter groups - these get used by

 * adreno_perfcounter_get and adreno_perfcounter_put

 */



static struct adreno_perfcount_register a3xx_perfcounters_cp[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_CP_0_LO,

		A3XX_RBBM_PERFCTR_CP_0_HI, 0, A3XX_CP_PERFCOUNTER_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_rbbm[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_0_LO,

		A3XX_RBBM_PERFCTR_RBBM_0_HI, 1, A3XX_RBBM_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RBBM_1_LO,

		A3XX_RBBM_PERFCTR_RBBM_1_HI, 2, A3XX_RBBM_PERFCOUNTER1_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_pc[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_0_LO,

		A3XX_RBBM_PERFCTR_PC_0_HI, 3, A3XX_PC_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_1_LO,

		A3XX_RBBM_PERFCTR_PC_1_HI, 4, A3XX_PC_PERFCOUNTER1_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_2_LO,

		A3XX_RBBM_PERFCTR_PC_2_HI, 5, A3XX_PC_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PC_3_LO,

		A3XX_RBBM_PERFCTR_PC_3_HI, 6, A3XX_PC_PERFCOUNTER3_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_vfd[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_0_LO,

		A3XX_RBBM_PERFCTR_VFD_0_HI, 7, A3XX_VFD_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VFD_1_LO,

		A3XX_RBBM_PERFCTR_VFD_1_HI, 8, A3XX_VFD_PERFCOUNTER1_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_hlsq[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_0_LO,

		A3XX_RBBM_PERFCTR_HLSQ_0_HI, 9,

		A3XX_HLSQ_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_1_LO,

		A3XX_RBBM_PERFCTR_HLSQ_1_HI, 10,

		A3XX_HLSQ_PERFCOUNTER1_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_2_LO,

		A3XX_RBBM_PERFCTR_HLSQ_2_HI, 11,

		A3XX_HLSQ_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_3_LO,

		A3XX_RBBM_PERFCTR_HLSQ_3_HI, 12,

		A3XX_HLSQ_PERFCOUNTER3_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_4_LO,

		A3XX_RBBM_PERFCTR_HLSQ_4_HI, 13,

		A3XX_HLSQ_PERFCOUNTER4_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_HLSQ_5_LO,

		A3XX_RBBM_PERFCTR_HLSQ_5_HI, 14,

		A3XX_HLSQ_PERFCOUNTER5_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_vpc[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_0_LO,

		A3XX_RBBM_PERFCTR_VPC_0_HI, 15, A3XX_VPC_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_VPC_1_LO,

		A3XX_RBBM_PERFCTR_VPC_1_HI, 16, A3XX_VPC_PERFCOUNTER1_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_tse[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_0_LO,

		A3XX_RBBM_PERFCTR_TSE_0_HI, 17, A3XX_GRAS_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TSE_1_LO,

		A3XX_RBBM_PERFCTR_TSE_1_HI, 18, A3XX_GRAS_PERFCOUNTER1_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_ras[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_0_LO,

		A3XX_RBBM_PERFCTR_RAS_0_HI, 19, A3XX_GRAS_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RAS_1_LO,

		A3XX_RBBM_PERFCTR_RAS_1_HI, 20, A3XX_GRAS_PERFCOUNTER3_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_uche[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_0_LO,

		A3XX_RBBM_PERFCTR_UCHE_0_HI, 21,

		A3XX_UCHE_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_1_LO,

		A3XX_RBBM_PERFCTR_UCHE_1_HI, 22,

		A3XX_UCHE_PERFCOUNTER1_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_2_LO,

		A3XX_RBBM_PERFCTR_UCHE_2_HI, 23,

		A3XX_UCHE_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_3_LO,

		A3XX_RBBM_PERFCTR_UCHE_3_HI, 24,

		A3XX_UCHE_PERFCOUNTER3_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_4_LO,

		A3XX_RBBM_PERFCTR_UCHE_4_HI, 25,

		A3XX_UCHE_PERFCOUNTER4_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_UCHE_5_LO,

		A3XX_RBBM_PERFCTR_UCHE_5_HI, 26,

		A3XX_UCHE_PERFCOUNTER5_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_tp[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_0_LO,

		A3XX_RBBM_PERFCTR_TP_0_HI, 27, A3XX_TP_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_1_LO,

		A3XX_RBBM_PERFCTR_TP_1_HI, 28, A3XX_TP_PERFCOUNTER1_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_2_LO,

		A3XX_RBBM_PERFCTR_TP_2_HI, 29, A3XX_TP_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_3_LO,

		A3XX_RBBM_PERFCTR_TP_3_HI, 30, A3XX_TP_PERFCOUNTER3_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_4_LO,

		A3XX_RBBM_PERFCTR_TP_4_HI, 31, A3XX_TP_PERFCOUNTER4_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_TP_5_LO,

		A3XX_RBBM_PERFCTR_TP_5_HI, 32, A3XX_TP_PERFCOUNTER5_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_sp[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_0_LO,

		A3XX_RBBM_PERFCTR_SP_0_HI, 33, A3XX_SP_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_1_LO,

		A3XX_RBBM_PERFCTR_SP_1_HI, 34, A3XX_SP_PERFCOUNTER1_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_2_LO,

		A3XX_RBBM_PERFCTR_SP_2_HI, 35, A3XX_SP_PERFCOUNTER2_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_3_LO,

		A3XX_RBBM_PERFCTR_SP_3_HI, 36, A3XX_SP_PERFCOUNTER3_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_4_LO,

		A3XX_RBBM_PERFCTR_SP_4_HI, 37, A3XX_SP_PERFCOUNTER4_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_5_LO,

		A3XX_RBBM_PERFCTR_SP_5_HI, 38, A3XX_SP_PERFCOUNTER5_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_6_LO,

		A3XX_RBBM_PERFCTR_SP_6_HI, 39, A3XX_SP_PERFCOUNTER6_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_SP_7_LO,

		A3XX_RBBM_PERFCTR_SP_7_HI, 40, A3XX_SP_PERFCOUNTER7_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_rb[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_0_LO,

		A3XX_RBBM_PERFCTR_RB_0_HI, 41, A3XX_RB_PERFCOUNTER0_SELECT },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_RB_1_LO,

		A3XX_RBBM_PERFCTR_RB_1_HI, 42, A3XX_RB_PERFCOUNTER1_SELECT },

};



static struct adreno_perfcount_register a3xx_perfcounters_pwr[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_RBBM_PERFCTR_PWR_0_LO,

		A3XX_RBBM_PERFCTR_PWR_0_HI, -1, 0 },

	/*

	 * A3XX_RBBM_PERFCTR_PWR_1_LO is used for frequency scaling and removed

	 * from the pool of available counters

	 */

};



static struct adreno_perfcount_register a3xx_perfcounters_vbif2[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW0,

		A3XX_VBIF2_PERF_CNT_HIGH0, -1, A3XX_VBIF2_PERF_CNT_SEL0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW1,

		A3XX_VBIF2_PERF_CNT_HIGH1, -1, A3XX_VBIF2_PERF_CNT_SEL1 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW2,

		A3XX_VBIF2_PERF_CNT_HIGH2, -1, A3XX_VBIF2_PERF_CNT_SEL2 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0, 0, A3XX_VBIF2_PERF_CNT_LOW3,

		A3XX_VBIF2_PERF_CNT_HIGH3, -1, A3XX_VBIF2_PERF_CNT_SEL3 },

};

/*

 * Placing EN register in select field since vbif perf counters

 * dont have select register to program

 */

static struct adreno_perfcount_register a3xx_perfcounters_vbif2_pwr[] = {

	{ KGSL_PERFCOUNTER_NOT_USED, 0,

		0, A3XX_VBIF2_PERF_PWR_CNT_LOW0,

		A3XX_VBIF2_PERF_PWR_CNT_HIGH0, -1,

		A3XX_VBIF2_PERF_PWR_CNT_EN0 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0,

		0, A3XX_VBIF2_PERF_PWR_CNT_LOW1,

		A3XX_VBIF2_PERF_PWR_CNT_HIGH1, -1,

		A3XX_VBIF2_PERF_PWR_CNT_EN1 },

	{ KGSL_PERFCOUNTER_NOT_USED, 0,

		0, A3XX_VBIF2_PERF_PWR_CNT_LOW2,

		A3XX_VBIF2_PERF_PWR_CNT_HIGH2, -1,

		A3XX_VBIF2_PERF_PWR_CNT_EN2 },

};



#define A3XX_PERFCOUNTER_GROUP(offset, name) \

	ADRENO_PERFCOUNTER_GROUP(a3xx, offset, name)



#define A3XX_PERFCOUNTER_GROUP_FLAGS(offset, name, flags) \

	ADRENO_PERFCOUNTER_GROUP_FLAGS(a3xx, offset, name, flags)



static struct adreno_perfcount_group a3xx_perfcounter_groups[] = {

	A3XX_PERFCOUNTER_GROUP(CP, cp),

	A3XX_PERFCOUNTER_GROUP(RBBM, rbbm),

	A3XX_PERFCOUNTER_GROUP(PC, pc),

	A3XX_PERFCOUNTER_GROUP(VFD, vfd),

	A3XX_PERFCOUNTER_GROUP(HLSQ, hlsq),

	A3XX_PERFCOUNTER_GROUP(VPC, vpc),

	A3XX_PERFCOUNTER_GROUP(TSE, tse),

	A3XX_PERFCOUNTER_GROUP(RAS, ras),

	A3XX_PERFCOUNTER_GROUP(UCHE, uche),

	A3XX_PERFCOUNTER_GROUP(TP, tp),

	A3XX_PERFCOUNTER_GROUP(SP, sp),

	A3XX_PERFCOUNTER_GROUP(RB, rb),

	A3XX_PERFCOUNTER_GROUP_FLAGS(PWR, pwr,

		ADRENO_PERFCOUNTER_GROUP_FIXED),

	A3XX_PERFCOUNTER_GROUP(VBIF, vbif2),

	A3XX_PERFCOUNTER_GROUP_FLAGS(VBIF_PWR, vbif2_pwr,

		ADRENO_PERFCOUNTER_GROUP_FIXED),

};



static struct adreno_perfcounters a3xx_perfcounters = {

	a3xx_perfcounter_groups,

	ARRAY_SIZE(a3xx_perfcounter_groups),

};



static struct adreno_ft_perf_counters a3xx_ft_perf_counters[] = {

	{KGSL_PERFCOUNTER_GROUP_SP, SP_ALU_ACTIVE_CYCLES},

	{KGSL_PERFCOUNTER_GROUP_SP, SP0_ICL1_MISSES},
@@ -1220,7 +1012,6 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_CP_MEQ_DATA, A3XX_CP_MEQ_DATA),

	ADRENO_REG_DEFINE(ADRENO_REG_CP_PROTECT_REG_0, A3XX_CP_PROTECT_REG_0),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A3XX_RBBM_STATUS),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_CTL, A3XX_RBBM_PERFCTR_CTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0,

					A3XX_RBBM_PERFCTR_LOAD_CMD0),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD1,
@@ -1236,7 +1027,6 @@ static unsigned int a3xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { 
	ADRENO_REG_DEFINE(ADRENO_REG_SQ_INST_STORE_MANAGEMENT,

				A3XX_SQ_INST_STORE_MANAGEMENT),

	ADRENO_REG_DEFINE(ADRENO_REG_TP0_CHICKEN, A3XX_TP0_CHICKEN),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_RBBM_CTL, A3XX_RBBM_RBBM_CTL),

	ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SW_RESET_CMD, A3XX_RBBM_SW_RESET_CMD),

	ADRENO_REG_DEFINE(ADRENO_REG_UCHE_INVALIDATE0,

			A3XX_UCHE_CACHE_INVALIDATE0_REG),
@@ -1446,7 +1236,7 @@ struct adreno_gpudev adreno_a3xx_gpudev = { 
	.reg_offsets = a3xx_register_offsets,

	.ft_perf_counters = a3xx_ft_perf_counters,

	.ft_perf_counters_count = ARRAY_SIZE(a3xx_ft_perf_counters),

	.perfcounters = &a3xx_perfcounters,

	.perfcounters = &adreno_a3xx_perfcounters,

	.irq_handler = a3xx_irq_handler,

	.vbif_xin_halt_ctrl0_mask = A30X_VBIF_XIN_HALT_CTRL0_MASK,

	.probe = a3xx_probe,

drivers/gpu/msm/adreno_a3xx.h

+6 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2013-2016, 2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2013-2016, 2019-2020, The Linux Foundation. All rights reserved.

 */

#ifndef __A3XX_H

#define __A3XX_H
@@ -22,6 +22,8 @@ struct adreno_a3xx_core { 
	u32 vbif_count;

};



struct adreno_device;



/**

 * to_a3xx_core - return the a3xx specific GPU core struct

 * @adreno_dev: An Adreno GPU device handle
@@ -41,4 +43,7 @@ unsigned int a3xx_irq_pending(struct adreno_device *adreno_dev); 


void a3xx_snapshot(struct adreno_device *adreno_dev,

		struct kgsl_snapshot *snapshot);



extern struct adreno_perfcounters adreno_a3xx_perfcounters;



#endif /*__A3XX_H */

drivers/gpu/msm/adreno_a3xx_perfcounter.c

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