Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4b0dda4f authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge branch 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull perf fixes from Ingo Molnar:
 "Tooling fixes, plus add missing interval sampling to certain x86 PEBS
  events"

* 'perf-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  perf tools: Add trace/beauty/generated/ into .gitignore
  perf trace: Fix call-graph output
  x86/events/intel/ds: Add PERF_SAMPLE_PERIOD into PEBS_FREERUNNING_FLAGS
  perf record: Fix period option handling
  perf evsel: Fix period/freq terms setup
  tools headers: Synchoronize x86 features UAPI headers
  tools headers: Synchronize uapi/linux/sched.h
  tools headers: Sync {tools/,}arch/powerpc/include/uapi/asm/kvm.h
  tooling headers: Synchronize updated s390 kvm UAPI headers
  tools headers: Synchronize sound/asound.h
parents b3250aab 59410f5a

arch/x86/events/perf_event.h

+2 −1
Original line number Diff line number Diff line
@@ -93,7 +93,8 @@ struct amd_nb { 
	PERF_SAMPLE_ID | PERF_SAMPLE_CPU | PERF_SAMPLE_STREAM_ID | \

	PERF_SAMPLE_DATA_SRC | PERF_SAMPLE_IDENTIFIER | \

	PERF_SAMPLE_TRANSACTION | PERF_SAMPLE_PHYS_ADDR | \

	PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER)

	PERF_SAMPLE_REGS_INTR | PERF_SAMPLE_REGS_USER | \

	PERF_SAMPLE_PERIOD)



#define PEBS_REGS \

	(PERF_REG_X86_AX | \

tools/arch/powerpc/include/uapi/asm/kvm.h

+25 −0
Original line number Diff line number Diff line
@@ -443,6 +443,31 @@ struct kvm_ppc_rmmu_info { 
	__u32	ap_encodings[8];

};



/* For KVM_PPC_GET_CPU_CHAR */

struct kvm_ppc_cpu_char {

	__u64	character;		/* characteristics of the CPU */

	__u64	behaviour;		/* recommended software behaviour */

	__u64	character_mask;		/* valid bits in character */

	__u64	behaviour_mask;		/* valid bits in behaviour */

};



/*

 * Values for character and character_mask.

 * These are identical to the values used by H_GET_CPU_CHARACTERISTICS.

 */

#define KVM_PPC_CPU_CHAR_SPEC_BAR_ORI31		(1ULL << 63)

#define KVM_PPC_CPU_CHAR_BCCTRL_SERIALISED	(1ULL << 62)

#define KVM_PPC_CPU_CHAR_L1D_FLUSH_ORI30	(1ULL << 61)

#define KVM_PPC_CPU_CHAR_L1D_FLUSH_TRIG2	(1ULL << 60)

#define KVM_PPC_CPU_CHAR_L1D_THREAD_PRIV	(1ULL << 59)

#define KVM_PPC_CPU_CHAR_BR_HINT_HONOURED	(1ULL << 58)

#define KVM_PPC_CPU_CHAR_MTTRIG_THR_RECONF	(1ULL << 57)

#define KVM_PPC_CPU_CHAR_COUNT_CACHE_DIS	(1ULL << 56)



#define KVM_PPC_CPU_BEHAV_FAVOUR_SECURITY	(1ULL << 63)

#define KVM_PPC_CPU_BEHAV_L1D_FLUSH_PR		(1ULL << 62)

#define KVM_PPC_CPU_BEHAV_BNDS_CHK_SPEC_BAR	(1ULL << 61)



/* Per-vcpu XICS interrupt controller state */

#define KVM_REG_PPC_ICP_STATE	(KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c)

tools/arch/s390/include/uapi/asm/kvm.h

+4 −1
Original line number Diff line number Diff line
@@ -224,6 +224,7 @@ struct kvm_guest_debug_arch { 
#define KVM_SYNC_RICCB  (1UL << 7)

#define KVM_SYNC_FPRS   (1UL << 8)

#define KVM_SYNC_GSCB   (1UL << 9)

#define KVM_SYNC_BPBC   (1UL << 10)

/* length and alignment of the sdnx as a power of two */

#define SDNXC 8

#define SDNXL (1UL << SDNXC)
@@ -247,7 +248,9 @@ struct kvm_sync_regs { 
	};

	__u8  reserved[512];	/* for future vector expansion */

	__u32 fpc;		/* valid on KVM_SYNC_VRS or KVM_SYNC_FPRS */

	__u8 padding1[52];	/* riccb needs to be 64byte aligned */

	__u8 bpbc : 1;		/* bp mode */

	__u8 reserved2 : 7;

	__u8 padding1[51];	/* riccb needs to be 64byte aligned */

	__u8 riccb[64];		/* runtime instrumentation controls block */

	__u8 padding2[192];	/* sdnx needs to be 256byte aligned */

	union {

tools/arch/x86/include/asm/cpufeatures.h

+20 −4
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ 
/*

 * Defines x86 CPU feature bits

 */

#define NCAPINTS			18	   /* N 32-bit words worth of info */

#define NCAPINTS			19	   /* N 32-bit words worth of info */

#define NBUGINTS			1	   /* N 32-bit bug flags */



/*
@@ -203,12 +203,15 @@ 
#define X86_FEATURE_PROC_FEEDBACK	( 7*32+ 9) /* AMD ProcFeedbackInterface */

#define X86_FEATURE_SME			( 7*32+10) /* AMD Secure Memory Encryption */

#define X86_FEATURE_PTI			( 7*32+11) /* Kernel Page Table Isolation enabled */

#define X86_FEATURE_RETPOLINE		( 7*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */

#define X86_FEATURE_RETPOLINE_AMD	( 7*32+13) /* "" AMD Retpoline mitigation for Spectre variant 2 */

#define X86_FEATURE_INTEL_PPIN		( 7*32+14) /* Intel Processor Inventory Number */

#define X86_FEATURE_INTEL_PT		( 7*32+15) /* Intel Processor Trace */

#define X86_FEATURE_AVX512_4VNNIW	( 7*32+16) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4FMAPS	( 7*32+17) /* AVX-512 Multiply Accumulation Single precision */

#define X86_FEATURE_CDP_L2		( 7*32+15) /* Code and Data Prioritization L2 */



#define X86_FEATURE_MBA			( 7*32+18) /* Memory Bandwidth Allocation */

#define X86_FEATURE_RSB_CTXSW		( 7*32+19) /* "" Fill RSB on context switches */



#define X86_FEATURE_USE_IBPB		( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */



/* Virtualization flags: Linux defined, word 8 */

#define X86_FEATURE_TPR_SHADOW		( 8*32+ 0) /* Intel TPR Shadow */
@@ -243,6 +246,7 @@ 
#define X86_FEATURE_AVX512IFMA		( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */

#define X86_FEATURE_CLFLUSHOPT		( 9*32+23) /* CLFLUSHOPT instruction */

#define X86_FEATURE_CLWB		( 9*32+24) /* CLWB instruction */

#define X86_FEATURE_INTEL_PT		( 9*32+25) /* Intel Processor Trace */

#define X86_FEATURE_AVX512PF		( 9*32+26) /* AVX-512 Prefetch */

#define X86_FEATURE_AVX512ER		( 9*32+27) /* AVX-512 Exponential and Reciprocal */

#define X86_FEATURE_AVX512CD		( 9*32+28) /* AVX-512 Conflict Detection */
@@ -268,6 +272,9 @@ 
#define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */

#define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */

#define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */

#define X86_FEATURE_IBPB		(13*32+12) /* Indirect Branch Prediction Barrier */

#define X86_FEATURE_IBRS		(13*32+14) /* Indirect Branch Restricted Speculation */

#define X86_FEATURE_STIBP		(13*32+15) /* Single Thread Indirect Branch Predictors */



/* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */

#define X86_FEATURE_DTHERM		(14*32+ 0) /* Digital Thermal Sensor */
@@ -316,6 +323,13 @@ 
#define X86_FEATURE_SUCCOR		(17*32+ 1) /* Uncorrectable error containment and recovery */

#define X86_FEATURE_SMCA		(17*32+ 3) /* Scalable MCA */



/* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */

#define X86_FEATURE_AVX512_4VNNIW	(18*32+ 2) /* AVX-512 Neural Network Instructions */

#define X86_FEATURE_AVX512_4FMAPS	(18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */

#define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */

#define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */

#define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */



/*

 * BUG word(s)

 */
@@ -342,5 +356,7 @@ 
#define X86_BUG_MONITOR			X86_BUG(12) /* IPI required to wake up remote CPU */

#define X86_BUG_AMD_E400		X86_BUG(13) /* CPU is among the affected by Erratum 400 */

#define X86_BUG_CPU_MELTDOWN		X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */

#define X86_BUG_SPECTRE_V1		X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */

#define X86_BUG_SPECTRE_V2		X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */



#endif /* _ASM_X86_CPUFEATURES_H */

tools/arch/x86/include/asm/disabled-features.h

+2 −1
Original line number Diff line number Diff line
@@ -77,6 +77,7 @@ 
#define DISABLED_MASK15	0

#define DISABLED_MASK16	(DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP)

#define DISABLED_MASK17	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18)

#define DISABLED_MASK18	0

#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 19)



#endif /* _ASM_X86_DISABLED_FEATURES_H */