Loading monaco-camera-sensor-idp.dtsi +10 −11 Original line number Diff line number Diff line Loading @@ -14,8 +14,8 @@ cam_vaf-supply = <&L7C>; regulator-names = "cam_vaf"; rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <2800000>; rgltr-min-voltage = <3000000>; rgltr-max-voltage = <3000000>; rgltr-load-current = <100000>; status = "ok"; }; Loading @@ -26,15 +26,14 @@ cam_vio-supply = <&L3C>; cam_vana-supply = <&L5C>; cam_vdig-supply = <&L1C>; cam_vaf-supply = <&L7C>; cam_clk-supply = <&gcc_camss_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk", "cam_vaf"; "cam_clk"; rgltr-cntrl-support; pwm-switch; rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; rgltr-load-current = <2500 50000 180000 0 125000>; rgltr-min-voltage = <1800000 2800000 1200000 0>; rgltr-max-voltage = <1800000 2800000 1200000 0>; rgltr-load-current = <2500 50000 180000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active Loading Loading @@ -98,7 +97,7 @@ cell-index = <0>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <0>; sensor-position-roll = <270>; sensor-position-roll = <90>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; actuator-src = <&actuator_rear>; Loading @@ -113,7 +112,7 @@ pwm-switch; rgltr-min-voltage = <1800000 2800000 1200000 0>; rgltr-max-voltage = <1800000 2800000 1200000 0>; rgltr-load-current = <2500 50000 180000 0 125000>; rgltr-load-current = <2500 50000 180000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active Loading Loading @@ -153,8 +152,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; rgltr-min-voltage = <1800000 2800000 1056000 0>; rgltr-max-voltage = <1800000 2800000 1056000 0>; rgltr-min-voltage = <1800000 2800000 1200000 0>; rgltr-max-voltage = <1800000 2800000 1200000 0>; rgltr-load-current = <3000 35000 80000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; Loading monaco-camera.dtsi +44 −43 Original line number Diff line number Diff line Loading @@ -6,6 +6,11 @@ status = "ok"; }; qcom,cam-sync { compatible = "qcom,cam-sync"; status = "ok"; }; cam_csiphy0: qcom,csiphy0 { cell-index = <0>; compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; Loading @@ -20,9 +25,9 @@ mipi-csi-vdd1-supply = <&L12A>; mipi-csi-vdd2-supply = <&L9A>; rgltr-cntrl-support; rgltr-min-voltage = <0 0 900000 1200000>; rgltr-max-voltage = <0 0 900000 1200000>; rgltr-load-current = <0 0 126000 74000>; rgltr-min-voltage = <0 904000 1232000>; rgltr-max-voltage = <0 904000 1232000>; rgltr-load-current = <0 126000 74000>; clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_CPHY_0_CLK>, <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, Loading Loading @@ -54,9 +59,9 @@ mipi-csi-vdd1-supply = <&L12A>; mipi-csi-vdd2-supply = <&L9A>; rgltr-cntrl-support; rgltr-min-voltage = <0 0 900000 1200000>; rgltr-max-voltage = <0 0 900000 1200000>; rgltr-load-current = <0 0 126000 74000>; rgltr-min-voltage = <0 904000 1232000>; rgltr-max-voltage = <0 904000 1232000>; rgltr-load-current = <0 126000 74000>; clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_CPHY_1_CLK>, <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, Loading Loading @@ -253,7 +258,6 @@ regulator-names = "camss-vdd"; camss-vdd-supply = <&gcc_camss_top_gdsc>; clock-names = "gcc_camss_ahb_clk", "gcc_camss_top_ahb_clk", "gcc_camss_top_ahb_clk_src", "gcc_camss_axi_clk", Loading @@ -261,7 +265,6 @@ "gcc_camss_nrt_axi_clk", "gcc_camss_rt_axi_clk"; clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, <&gcc GCC_CAMSS_AXI_CLK>, Loading @@ -270,15 +273,12 @@ <&gcc GCC_CAMSS_RT_AXI_CLK>; src-clock-name = "gcc_camss_axi_clk_src"; clock-rates = <0 0 0 0 0 0 0>, <0 0 80000000 0 19200000 0 0>, <0 0 80000000 0 150000000 0 0>, <0 0 80000000 0 200000000 0 0>, <0 0 80000000 0 300000000 0 0>, <0 0 80000000 0 300000000 0 0>, <0 0 80000000 0 300000000 0 0>; clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; <0 0 0 0 0 0>, <0 19200000 0 19200000 0 0>, <0 80000000 0 150000000 0 0>, <0 80000000 0 300000000 0 0>, <0 80000000 0 300000000 0 0>; clock-cntl-level = "suspend", "lowsvs", "svs", "nominal", "turbo"; qcom,cx-ipeak-gpu-limit = <921600000>; control-camnoc-axi-clk; camnoc-bus-width = <32>; Loading Loading @@ -502,10 +502,9 @@ <&gcc GCC_CAMSS_OPE_CLK_SRC>, <&gcc GCC_CAMSS_OPE_CLK>; clock-rates = <0 0 0>, <0 0 0>, <0 0 0>, <0 0 0>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "turbo"; cdm-client-names = "ope"; config-fifo; fifo-depths = <64 64 64 64>; Loading Loading @@ -545,10 +544,11 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = <240000000 0 0 0 256000000 0>, <384000000 0 0 0 460800000 0>, <426400000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; <19200000 0 19200000 0 19200000 0>, <256000000 0 256000000 0 288000000 0>, <384000000 0 384000000 0 576000000 0>, <426400000 0 384000000 0 576000000 0>; clock-cntl-level = "lowsvs", "svs", "nominal", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; ppi-enable; Loading @@ -572,10 +572,10 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = <256000000 0>, <460800000 0>, <19200000 0>, <288000000 0>, <576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <4>; Loading Loading @@ -609,10 +609,11 @@ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = <240000000 0 240000000 0 256000000 0>, <384000000 0 341333333 0 460800000 0>, <426400000 0 384000000 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; <19200000 0 19200000 0 19200000 0>, <256000000 0 256000000 0 288000000 0>, <384000000 0 384000000 0 576000000 0>, <426000000 0 384000000 0 576000000 0>; clock-cntl-level = "lowsvs", "svs", "nominal", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; ppi-enable; Loading @@ -636,10 +637,10 @@ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = <256000000 0>, <460800000 0>, <19200000 0>, <288000000 0>, <576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <5>; Loading Loading @@ -694,10 +695,10 @@ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, <&gcc GCC_CAMSS_CPHY_0_CLK>; clock-rates = <240000000 0 0>, <341333333 0 0>, <19200000 0 0>, <256000000 0 0>, <384000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "turbo"; src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; status = "ok"; Loading @@ -721,10 +722,10 @@ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, <&gcc GCC_CAMSS_CPHY_1_CLK>; clock-rates = <240000000 0 0>, <341333333 0 0>, <19200000 0 0>, <256000000 0 0>, <384000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "turbo"; src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; status = "ok"; Loading Loading @@ -770,11 +771,11 @@ <&gcc GCC_CAMSS_OPE_CLK_SRC>, <&gcc GCC_CAMSS_OPE_CLK>; clock-rates = <19200000 0 19200000 0>, <171428571 0 200000000 0>, <171428571 0 266600000 0>, <240000000 0 465000000 0>, <240000000 0 580000000 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; clock-cntl-level = "lowsvs", "svs", "nominal", "turbo"; src-clock-name = "ope_clk_src"; status = "ok"; }; Loading Loading
monaco-camera-sensor-idp.dtsi +10 −11 Original line number Diff line number Diff line Loading @@ -14,8 +14,8 @@ cam_vaf-supply = <&L7C>; regulator-names = "cam_vaf"; rgltr-cntrl-support; rgltr-min-voltage = <2800000>; rgltr-max-voltage = <2800000>; rgltr-min-voltage = <3000000>; rgltr-max-voltage = <3000000>; rgltr-load-current = <100000>; status = "ok"; }; Loading @@ -26,15 +26,14 @@ cam_vio-supply = <&L3C>; cam_vana-supply = <&L5C>; cam_vdig-supply = <&L1C>; cam_vaf-supply = <&L7C>; cam_clk-supply = <&gcc_camss_top_gdsc>; regulator-names = "cam_vio", "cam_vana", "cam_vdig", "cam_clk", "cam_vaf"; "cam_clk"; rgltr-cntrl-support; pwm-switch; rgltr-min-voltage = <1800000 2800000 1200000 0 2800000>; rgltr-max-voltage = <1800000 2800000 1200000 0 2800000>; rgltr-load-current = <2500 50000 180000 0 125000>; rgltr-min-voltage = <1800000 2800000 1200000 0>; rgltr-max-voltage = <1800000 2800000 1200000 0>; rgltr-load-current = <2500 50000 180000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active Loading Loading @@ -98,7 +97,7 @@ cell-index = <0>; compatible = "qcom,cam-sensor"; csiphy-sd-index = <0>; sensor-position-roll = <270>; sensor-position-roll = <90>; sensor-position-pitch = <0>; sensor-position-yaw = <180>; actuator-src = <&actuator_rear>; Loading @@ -113,7 +112,7 @@ pwm-switch; rgltr-min-voltage = <1800000 2800000 1200000 0>; rgltr-max-voltage = <1800000 2800000 1200000 0>; rgltr-load-current = <2500 50000 180000 0 125000>; rgltr-load-current = <2500 50000 180000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; pinctrl-0 = <&cam_sensor_mclk0_active Loading Loading @@ -153,8 +152,8 @@ "cam_clk"; rgltr-cntrl-support; pwm-switch; rgltr-min-voltage = <1800000 2800000 1056000 0>; rgltr-max-voltage = <1800000 2800000 1056000 0>; rgltr-min-voltage = <1800000 2800000 1200000 0>; rgltr-max-voltage = <1800000 2800000 1200000 0>; rgltr-load-current = <3000 35000 80000 0>; gpio-no-mux = <0>; pinctrl-names = "cam_default", "cam_suspend"; Loading
monaco-camera.dtsi +44 −43 Original line number Diff line number Diff line Loading @@ -6,6 +6,11 @@ status = "ok"; }; qcom,cam-sync { compatible = "qcom,cam-sync"; status = "ok"; }; cam_csiphy0: qcom,csiphy0 { cell-index = <0>; compatible = "qcom,csiphy-v1.2.3", "qcom,csiphy"; Loading @@ -20,9 +25,9 @@ mipi-csi-vdd1-supply = <&L12A>; mipi-csi-vdd2-supply = <&L9A>; rgltr-cntrl-support; rgltr-min-voltage = <0 0 900000 1200000>; rgltr-max-voltage = <0 0 900000 1200000>; rgltr-load-current = <0 0 126000 74000>; rgltr-min-voltage = <0 904000 1232000>; rgltr-max-voltage = <0 904000 1232000>; rgltr-load-current = <0 126000 74000>; clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_CPHY_0_CLK>, <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK_SRC>, Loading Loading @@ -54,9 +59,9 @@ mipi-csi-vdd1-supply = <&L12A>; mipi-csi-vdd2-supply = <&L9A>; rgltr-cntrl-support; rgltr-min-voltage = <0 0 900000 1200000>; rgltr-max-voltage = <0 0 900000 1200000>; rgltr-load-current = <0 0 126000 74000>; rgltr-min-voltage = <0 904000 1232000>; rgltr-max-voltage = <0 904000 1232000>; rgltr-load-current = <0 126000 74000>; clocks = <&gcc GCC_CAMSS_TFE_CPHY_RX_CLK_SRC>, <&gcc GCC_CAMSS_CPHY_1_CLK>, <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK_SRC>, Loading Loading @@ -253,7 +258,6 @@ regulator-names = "camss-vdd"; camss-vdd-supply = <&gcc_camss_top_gdsc>; clock-names = "gcc_camss_ahb_clk", "gcc_camss_top_ahb_clk", "gcc_camss_top_ahb_clk_src", "gcc_camss_axi_clk", Loading @@ -261,7 +265,6 @@ "gcc_camss_nrt_axi_clk", "gcc_camss_rt_axi_clk"; clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK>, <&gcc GCC_CAMSS_TOP_AHB_CLK_SRC>, <&gcc GCC_CAMSS_AXI_CLK>, Loading @@ -270,15 +273,12 @@ <&gcc GCC_CAMSS_RT_AXI_CLK>; src-clock-name = "gcc_camss_axi_clk_src"; clock-rates = <0 0 0 0 0 0 0>, <0 0 80000000 0 19200000 0 0>, <0 0 80000000 0 150000000 0 0>, <0 0 80000000 0 200000000 0 0>, <0 0 80000000 0 300000000 0 0>, <0 0 80000000 0 300000000 0 0>, <0 0 80000000 0 300000000 0 0>; clock-cntl-level = "suspend", "minsvs", "lowsvs", "svs", "svs_l1", "nominal", "turbo"; <0 0 0 0 0 0>, <0 19200000 0 19200000 0 0>, <0 80000000 0 150000000 0 0>, <0 80000000 0 300000000 0 0>, <0 80000000 0 300000000 0 0>; clock-cntl-level = "suspend", "lowsvs", "svs", "nominal", "turbo"; qcom,cx-ipeak-gpu-limit = <921600000>; control-camnoc-axi-clk; camnoc-bus-width = <32>; Loading Loading @@ -502,10 +502,9 @@ <&gcc GCC_CAMSS_OPE_CLK_SRC>, <&gcc GCC_CAMSS_OPE_CLK>; clock-rates = <0 0 0>, <0 0 0>, <0 0 0>, <0 0 0>; clock-cntl-level = "lowsvs", "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "turbo"; cdm-client-names = "ope"; config-fifo; fifo-depths = <64 64 64 64>; Loading Loading @@ -545,10 +544,11 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = <240000000 0 0 0 256000000 0>, <384000000 0 0 0 460800000 0>, <426400000 0 0 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; <19200000 0 19200000 0 19200000 0>, <256000000 0 256000000 0 288000000 0>, <384000000 0 384000000 0 576000000 0>, <426400000 0 384000000 0 576000000 0>; clock-cntl-level = "lowsvs", "svs", "nominal", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; ppi-enable; Loading @@ -572,10 +572,10 @@ <&gcc GCC_CAMSS_TFE_0_CLK_SRC>, <&gcc GCC_CAMSS_TFE_0_CLK>; clock-rates = <256000000 0>, <460800000 0>, <19200000 0>, <288000000 0>, <576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <4>; Loading Loading @@ -609,10 +609,11 @@ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = <240000000 0 240000000 0 256000000 0>, <384000000 0 341333333 0 460800000 0>, <426400000 0 384000000 0 576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; <19200000 0 19200000 0 19200000 0>, <256000000 0 256000000 0 288000000 0>, <384000000 0 384000000 0 576000000 0>, <426000000 0 384000000 0 576000000 0>; clock-cntl-level = "lowsvs", "svs", "nominal", "turbo"; src-clock-name = "tfe_csid_clk_src"; clock-control-debugfs = "true"; ppi-enable; Loading @@ -636,10 +637,10 @@ <&gcc GCC_CAMSS_TFE_1_CLK_SRC>, <&gcc GCC_CAMSS_TFE_1_CLK>; clock-rates = <256000000 0>, <460800000 0>, <19200000 0>, <288000000 0>, <576000000 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "turbo"; src-clock-name = "tfe_clk_src"; clock-control-debugfs = "true"; cam_hw_pid = <5>; Loading Loading @@ -694,10 +695,10 @@ <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, <&gcc GCC_CAMSS_CPHY_0_CLK>; clock-rates = <240000000 0 0>, <341333333 0 0>, <19200000 0 0>, <256000000 0 0>, <384000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "turbo"; src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; status = "ok"; Loading @@ -721,10 +722,10 @@ <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>, <&gcc GCC_CAMSS_CPHY_1_CLK>; clock-rates = <240000000 0 0>, <341333333 0 0>, <19200000 0 0>, <256000000 0 0>, <384000000 0 0>; clock-cntl-level = "svs", "svs_l1", "turbo"; clock-cntl-level = "lowsvs", "svs", "turbo"; src-clock-name = "cphy_rx_clk_src"; clock-control-debugfs = "false"; status = "ok"; Loading Loading @@ -770,11 +771,11 @@ <&gcc GCC_CAMSS_OPE_CLK_SRC>, <&gcc GCC_CAMSS_OPE_CLK>; clock-rates = <19200000 0 19200000 0>, <171428571 0 200000000 0>, <171428571 0 266600000 0>, <240000000 0 465000000 0>, <240000000 0 580000000 0>; clock-cntl-level = "svs", "svs_l1", "nominal", "turbo"; clock-cntl-level = "lowsvs", "svs", "nominal", "turbo"; src-clock-name = "ope_clk_src"; status = "ok"; }; Loading