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Commit 4a7bc07f authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

ARM: dts: exynos: Add GPU/Mali 400 node to Exynos3250 



Add nodes for GPU (Mali 400) to Exynos3250.  This is still limited and
not tested:
1. No dynamic voltage and frequency scaling,
2. Not sure what to do with CLK_G3D clock responsible for gating entire
   IP block (it is now being disabled as unused).

Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent 8b388cee

arch/arm/boot/dts/exynos3250-artik5.dtsi

+5 −0
Original line number Diff line number Diff line
@@ -59,6 +59,11 @@ 
	cpu0-supply = <&buck2_reg>;

};



&gpu {

	mali-supply = <&buck3_reg>;

	status = "okay";

};



&i2c_0 {

	#address-cells = <1>;

	#size-cells = <0>;

arch/arm/boot/dts/exynos3250-monk.dts

+5 −0
Original line number Diff line number Diff line
@@ -172,6 +172,11 @@ 
	status = "okay";

};



&gpu {

	mali-supply = <&buck3_reg>;

	status = "okay";

};



&hsotg {

	vusb_d-supply = <&ldo15_reg>;

	vusb_a-supply = <&ldo12_reg>;

arch/arm/boot/dts/exynos3250-rinato.dts

+5 −0
Original line number Diff line number Diff line
@@ -244,6 +244,11 @@ 
	};

};



&gpu {

	mali-supply = <&buck3_reg>;

	status = "okay";

};



&i2c_0 {

	#address-cells = <1>;

	#size-cells = <0>;

arch/arm/boot/dts/exynos3250.dtsi

+33 −0
Original line number Diff line number Diff line
@@ -126,6 +126,39 @@ 
		};

	};



	gpu: gpu@13000000 {

		compatible = "samsung,exynos4210-mali", "arm,mali-400";

		reg = <0x13000000 0x10000>;

		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,

			     <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;

		interrupt-names = "gp",

				  "gpmmu",

				  "pp0",

				  "ppmmu0",

				  "pp1",

				  "ppmmu1",

				  "pp2",

				  "ppmmu2",

				  "pp3",

				  "ppmmu3",

				  "pmu";

		clocks = <&cmu CLK_G3D>,

			 <&cmu CLK_SCLK_G3D>;

		clock-names = "bus", "core";

		power-domains = <&pd_g3d>;

		status = "disabled";

		/* TODO: operating points for DVFS, assigned clock as 134 MHz */

	};



	pmu {

		compatible = "arm,cortex-a7-pmu";

		interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,