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Commit 4a706964 authored by Hui Li's avatar Hui Li
Browse files

ARM: dts: msm: Add support for kgsl driver on SA6155 

Add support for GPU driver to perform graphics functionality on SA6155.

Change-Id: I052d3434203f8d7f2da6d3ab19c890f26b405e42
parent fafa8068

qcom/sa6155.dtsi

+338 −0
Original line number Diff line number Diff line
@@ -61,3 +61,341 @@ 
&slpi_tlmm {

	status = "ok";

};



/* GPU power level overrides */

&msm_gpu {

	/*

	 * Speed-bin zero is default speed bin.

	 * For rest of the speed bins, speed-bin value

	 * is calulated as FMAX/4.8 MHz round up to zero

	 * decimal places.

	 */



	/delete-node/qcom,gpu-pwrlevel-bins;

	qcom,gpu-pwrlevel-bins {

		#address-cells = <1>;

		#size-cells = <0>;



		compatible="qcom,gpu-pwrlevel-bins";



		qcom,gpu-pwrlevels-0 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <0>;



			qcom,initial-pwrlevel = <4>;

			qcom,ca-target-pwrlevel = <3>;



			/* TURBO */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <845000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;

				qcom,bus-freq = <11>;

				qcom,bus-min = <10>;

				qcom,bus-max = <11>;

			};



			/* NOM L1 */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <745000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

				qcom,bus-freq = <10>;

				qcom,bus-min = <9>;

				qcom,bus-max = <11>;

			};



			/* NOM */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};



			/* SVS L1 */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <500000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <435000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};



		qcom,gpu-pwrlevels-1 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <177>;



			qcom,initial-pwrlevel = <4>;

			qcom,ca-target-pwrlevel = <3>;



			/* TURBO */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <845000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;

				qcom,bus-freq = <11>;

				qcom,bus-min = <10>;

				qcom,bus-max = <11>;

			};



			/* NOM L1 */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <745000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

				qcom,bus-freq = <10>;

				qcom,bus-min = <9>;

				qcom,bus-max = <11>;

			};



			/* NOM */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};



			/* SVS L1 */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <500000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <435000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};



		qcom,gpu-pwrlevels-2 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <156>;



			qcom,initial-pwrlevel = <3>;

			qcom,ca-target-pwrlevel = <2>;



			/* NOM L1 */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <745000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

				qcom,bus-freq = <11>;

				qcom,bus-min = <10>;

				qcom,bus-max = <11>;

			};



			/* NOM */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};



			/* SVS L1 */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <500000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <435000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};



		qcom,gpu-pwrlevels-3 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <136>;



			qcom,initial-pwrlevel = <2>;

			qcom,ca-target-pwrlevel = <1>;



			/* NOM */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};



			/* SVS L1 */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <500000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <435000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};



		qcom,gpu-pwrlevels-4 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <105>;



			qcom,initial-pwrlevel = <1>;

			qcom,ca-target-pwrlevel = <0>;



			/* SVS L1 */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <500000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <435000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};



		qcom,gpu-pwrlevels-5 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <73>;



			qcom,initial-pwrlevel = <0>;

			qcom,ca-target-pwrlevel = <0>;



			/* SVS */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <350000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};

	};

};

qcom/sa6155p.dtsi

+338 −0
Original line number Diff line number Diff line
@@ -79,3 +79,341 @@ 
&slpi_tlmm {

	status = "ok";

};



/* GPU power level overrides */

&msm_gpu {

	/*

	 * Speed-bin zero is default speed bin.

	 * For rest of the speed bins, speed-bin value

	 * is calulated as FMAX/4.8 MHz round up to zero

	 * decimal places.

	 */



	/delete-node/qcom,gpu-pwrlevel-bins;

	qcom,gpu-pwrlevel-bins {

		#address-cells = <1>;

		#size-cells = <0>;



		compatible="qcom,gpu-pwrlevel-bins";



		qcom,gpu-pwrlevels-0 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <0>;



			qcom,initial-pwrlevel = <4>;

			qcom,ca-target-pwrlevel = <3>;



			/* TURBO */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <845000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;

				qcom,bus-freq = <11>;

				qcom,bus-min = <10>;

				qcom,bus-max = <11>;

			};



			/* NOM L1 */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <745000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

				qcom,bus-freq = <10>;

				qcom,bus-min = <9>;

				qcom,bus-max = <11>;

			};



			/* NOM */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};



			/* SVS L1 */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <500000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <435000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};



		qcom,gpu-pwrlevels-1 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <177>;



			qcom,initial-pwrlevel = <4>;

			qcom,ca-target-pwrlevel = <3>;



			/* TURBO */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <845000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;

				qcom,bus-freq = <11>;

				qcom,bus-min = <10>;

				qcom,bus-max = <11>;

			};



			/* NOM L1 */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <745000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

				qcom,bus-freq = <10>;

				qcom,bus-min = <9>;

				qcom,bus-max = <11>;

			};



			/* NOM */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};



			/* SVS L1 */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <500000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <435000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@5 {

				reg = <5>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};



		qcom,gpu-pwrlevels-2 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <156>;



			qcom,initial-pwrlevel = <3>;

			qcom,ca-target-pwrlevel = <2>;



			/* NOM L1 */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <745000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;

				qcom,bus-freq = <11>;

				qcom,bus-min = <10>;

				qcom,bus-max = <11>;

			};



			/* NOM */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};



			/* SVS L1 */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <500000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <435000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@4 {

				reg = <4>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};



		qcom,gpu-pwrlevels-3 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <136>;



			qcom,initial-pwrlevel = <2>;

			qcom,ca-target-pwrlevel = <1>;



			/* NOM */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <650000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;

				qcom,bus-freq = <9>;

				qcom,bus-min = <8>;

				qcom,bus-max = <10>;

			};



			/* SVS L1 */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <500000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <435000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@3 {

				reg = <3>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};



		qcom,gpu-pwrlevels-4 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <105>;



			qcom,initial-pwrlevel = <1>;

			qcom,ca-target-pwrlevel = <0>;



			/* SVS L1 */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <500000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;

				qcom,bus-freq = <8>;

				qcom,bus-min = <7>;

				qcom,bus-max = <9>;

			};



			/* SVS */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <435000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@2 {

				reg = <2>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};



		qcom,gpu-pwrlevels-5 {

			#address-cells = <1>;

			#size-cells = <0>;



			qcom,speed-bin = <73>;



			qcom,initial-pwrlevel = <0>;

			qcom,ca-target-pwrlevel = <0>;



			/* SVS */

			qcom,gpu-pwrlevel@0 {

				reg = <0>;

				qcom,gpu-freq = <350000000>;

				qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;

				qcom,bus-freq = <7>;

				qcom,bus-min = <5>;

				qcom,bus-max = <8>;

			};



			/* XO */

			qcom,gpu-pwrlevel@1 {

				reg = <1>;

				qcom,gpu-freq = <0>;

				qcom,level = <RPMH_REGULATOR_LEVEL_RETENTION>;

				qcom,bus-freq = <0>;

				qcom,bus-min = <0>;

				qcom,bus-max = <0>;

			};

		};

	};

};

qcom/sm6150-gpu.dtsi

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+654 −0

File added.

Preview size limit exceeded, changes collapsed.

qcom/sm6150.dtsi

+1 −0
Original line number Diff line number Diff line
@@ -2367,5 +2367,6 @@ 


#include "msm-arm-smmu-sm6150.dtsi"

#include "sm6150-slpi-pinctrl.dtsi"

#include "sm6150-gpu.dtsi"

#include "sm6150-usb.dtsi"

#include "sm6150-vidc.dtsi"