Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 4a5dc080 authored by Hongwei Ren's avatar Hongwei Ren Committed by Yuxin Feng
Browse files

ARM: dts: msm: Add clock controller nodes for SCUBA 

Add GCC/GPUCC/DISPCC/DEBUGCC/RPMCC/GDSC clock controller
nodes for SCUBA and also add CPUFREQ HW node to scale the
cpu frequency.

Change-Id: Icb621342412e03d299d18f8cf05ba1f681c859b1
parent 0500ef9e

qcom/qrb2210-rb1-gdsc.dtsi

0 → 100644
+111 −0
Original line number Diff line number Diff line 
&soc {

	/* GDSCs in GCC */

	gcc_camss_top_gdsc: qcom,gdsc@1458004 {

		compatible = "qcom,gdsc";

		reg = <0x1458004 0x4>;

		regulator-name = "gcc_camss_top_gdsc";

		status = "disabled";

	};



	gcc_usb30_prim_gdsc: qcom,gdsc@141a004 {

		compatible = "qcom,gdsc";

		reg = <0x141a004 0x4>;

		regulator-name = "gcc_usb30_prim_gdsc";

		status = "disabled";

	};



	gcc_vcodec0_gdsc: qcom,gdsc@1458098 {

		compatible = "qcom,gdsc";

		reg = <0x1458098 0x4>;

		regulator-name = "gcc_vcodec0_gdsc";

		status = "disabled";

	};



	gcc_venus_gdsc: qcom,gdsc@145807c {

		compatible = "qcom,gdsc";

		reg = <0x145807c 0x4>;

		regulator-name = "gcc_venus_gdsc";

		status = "disabled";

	};



	hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc: qcom,gdsc@147d074 {

		compatible = "qcom,gdsc";

		reg = <0x147d074 0x4>;

		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc: qcom,gdsc@147d078 {

		compatible = "qcom,gdsc";

		reg = <0x147d078 0x4>;

		regulator-name = "hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_turing_mmu_tbu1_gdsc: qcom,gdsc@147d060 {

		compatible = "qcom,gdsc";

		reg = <0x147d060 0x4>;

		regulator-name = "hlos1_vote_turing_mmu_tbu1_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	hlos1_vote_turing_mmu_tbu0_gdsc: qcom,gdsc@147d07c {

		compatible = "qcom,gdsc";

		reg = <0x147d07c 0x4>;

		regulator-name = "hlos1_vote_turing_mmu_tbu0_gdsc";

		qcom,no-status-check-on-disable;

		qcom,gds-timeout = <500>;

		status = "disabled";

	};



	/* GDSCs in DISPCC */

	mdss_core_gdsc: qcom,gdsc@5f03000 {

		compatible = "qcom,gdsc";

		reg = <0x5f03000 0x4>;

		regulator-name = "mdss_core_gdsc";

		proxy-supply = <&mdss_core_gdsc>;

		qcom,proxy-consumer-enable;

		status = "disabled";

	};



	/* GDSCs in GPUCC */

	gpu_cx_hw_ctrl: syscon@5991540 {

		compatible = "syscon";

		reg = <0x5991540 0x4>;

	};



	gpu_gx_sw_reset: syscon@5991008 {

		compatible = "syscon";

		reg = <0x5991008 0x4>;

	};



	gpu_gx_domain_addr: syscon@5991508 {

		compatible = "syscon";

		reg = <0x5991508 0x4>;

	};



	gpu_cx_gdsc: qcom,gdsc@599106c {

		compatible = "qcom,gdsc";

		reg = <0x599106c 0x4>;

		regulator-name = "gpu_cx_gdsc";

		hw-ctl-addr = <&gpu_cx_hw_ctrl>;

		qcom,no-status-check-on-disable;

		status = "disabled";

	};



	gpu_gx_gdsc: qcom,gdsc@599100c {

		compatible = "qcom,gdsc";

		reg = <0x599100c 0x4>;

		regulator-name = "gpu_gx_gdsc";

		sw-reset = <&gpu_gx_sw_reset>;

		domain-addr = <&gpu_gx_domain_addr>;

		qcom,reset-aon-logic;

		status = "disabled";

	};

};

qcom/qrb2210-rb1-idp.dtsi

+2 −0
Original line number Diff line number Diff line 
#include <dt-bindings/clock/qcom,gcc-scuba.h>

#include <dt-bindings/clock/qcom,gpucc-scuba.h>

#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/iio/qcom,spmi-vadc.h>

#include "qrb2210-rb1-ion.dtsi"

qcom/qrb2210-rb1.dtsi

+143 −0
Original line number Diff line number Diff line
@@ -3,6 +3,10 @@ 
#include <dt-bindings/gpio/gpio.h>

#include <dt-bindings/spmi/spmi.h>

#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>

#include <dt-bindings/clock/qcom,gcc-scuba.h>

#include <dt-bindings/clock/qcom,gpucc-scuba.h>

#include <dt-bindings/clock/qcom,dispcc-scuba.h>

#include <dt-bindings/clock/qcom,rpmcc.h>



/ {

	model = "Qualcomm Technologies, Inc. Qrb2210 RB1";
@@ -41,6 +45,7 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;

			L2_0: l2-cache {

				compatible = "arm,arch-cache";

				cache-level = <2>;
@@ -63,6 +68,7 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;



			L1_I_1: l1-icache {

				compatible = "arm,arch-cache";
@@ -81,6 +87,7 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;



			L1_I_2: l1-icache {

				compatible = "arm,arch-cache";
@@ -99,6 +106,7 @@ 
			capacity-dmips-mhz = <1024>;

			dynamic-power-coefficient = <100>;

			next-level-cache = <&L2_0>;

			qcom,freq-domain = <&cpufreq_hw 0 4>;



			L1_I_3: l1-icache {

				compatible = "arm,arch-cache";
@@ -611,6 +619,93 @@ dcc: dcc_v2@1be2000 { 
		};

	};



	clocks {

		xo_board: xo-board {

			compatible = "fixed-clock";

			clock-frequency = <38400000>;

			clock-output-names = "xo_board";

			#clock-cells = <0>;

		};



		sleep_clk: sleep-clk {

			compatible = "fixed-clock";

			clock-frequency = <32764>;

			clock-output-names = "chip_sleep_clk";

			#clock-cells = <0>;

		};

	};



	rpmcc: qcom,rpmcc {

		compatible = "qcom,rpmcc-scuba";

		#clock-cells = <1>;

	};



	gcc: qcom,gcc@1400000 {

		compatible = "qcom,scuba-gcc", "syscon";

		reg = <0x1400000 0x1f0000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;

		vdd_mx-supply = <&VDD_MX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	dispcc: qcom,dispcc@5f00000 {

		compatible = "qcom,scuba-dispcc", "syscon";

		reg = <0x5f00000 0x20000>;

		reg-names = "cc_base";

		clock-names = "cfg_ahb_clk";

		clocks = <&gcc GCC_DISP_AHB_CLK>;

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	gpucc: qcom,gpucc@5990000 {

		compatible = "qcom,scuba-gpucc", "syscon";

		reg = <0x5990000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		/*qcom,gpu_cc_gx_gfx3d_clk_src-opp-handle = <&msm_gpu>;*/

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	mccc_debug: syscon@447d200 {

		compatible = "syscon";

		reg = <0x447d200 0x100>;

	};



	cpucc_debug: syscon@f11101c {

		compatible = "syscon";

		reg = <0xf11101c 0x4>;

	};



	debugcc: qcom,cc-debug {

		compatible = "qcom,scuba-debugcc";

		status = "disabled";

		qcom,gcc = <&gcc>;

		qcom,dispcc = <&dispcc>;

		qcom,gpucc = <&gpucc>;

		qcom,mccc = <&mccc_debug>;

		qcom,cpucc = <&cpucc_debug>;

		clock-names = "xo_clk_src";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;

		#clock-cells = <1>;

	};



	cpufreq_hw: qcom,cpufreq-hw {

		compatible = "qcom,cpufreq-hw";

		reg = <0xf521000 0x1400>;

		reg-names = "freq-domain0";

		clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;

		clock-names = "xo", "alternate";

		qcom,no-accumulative-counter;

		qcom,max-lut-entries = <12>;

		#freq-domain-cells = <2>;

	};



	spmi_bus: qcom,spmi@1c40000 {

		compatible = "qcom,spmi-pmic-arb";

		reg = <0x1c40000 0x1100>,
@@ -1050,6 +1145,8 @@ dcc: dcc_v2@1be2000 { 
#include "qrb2210-rb1-pinctrl.dtsi"

#include "qrb2210-rb1-ion.dtsi"

#include "msm-arm-smmu-qrb2210-rb1.dtsi"

#include "qrb2210-rb1-qupv3.dtsi"

#include "qrb2210-rb1-gdsc.dtsi"



&qupv3_se1_i2c {

	#address-cells = <1>;
@@ -1160,6 +1257,52 @@ dcc: dcc_v2@1be2000 { 
	};

};



&gcc_camss_top_gdsc {

	status = "ok";

};



&gcc_usb30_prim_gdsc {

	status = "ok";

};



&gcc_vcodec0_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&gcc_venus_gdsc {

	status = "ok";

};



&hlos1_vote_mm_snoc_mmu_tbu_rt_gdsc {

	status = "ok";

};



&hlos1_vote_mm_snoc_mmu_tbu_nrt_gdsc {

	status = "ok";

};



&hlos1_vote_turing_mmu_tbu1_gdsc {

	status = "ok";

};



&hlos1_vote_turing_mmu_tbu0_gdsc {

	status = "ok";

};



&mdss_core_gdsc {

	qcom,support-hw-trigger;

	status = "ok";

};



&gpu_cx_gdsc {

	status = "ok";

};



&gpu_gx_gdsc {

	status = "ok";

};



&pm2250_vadc {

	#address-cells = <1>;

	#size-cells = <0>;