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Commit 4a3d3f67 authored by Chris Wilson's avatar Chris Wilson
Browse files

drm/i915: Match code to comment and enforce ppgtt for execlists 



Our execlist dispatch code requires a ppGTT so make sure we enforce that
option in intel_sanitize_enable_ppgtt(). The comment already tries to
explain that execlists requires ppgtt, but was written when gen8 may
have also taken the legacy path; so rewrite the code to match the
comment by using HAS_EXECLISTS() feature instead of the gen.

Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Reviewed-by: default avatarJoonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180922141804.21183-1-chris@chris-wilson.co.uk
parent 570b16b5

drivers/gpu/drm/i915/i915_gem_gtt.c

+2 −2
Original line number Diff line number Diff line
@@ -152,10 +152,10 @@ int intel_sanitize_enable_ppgtt(struct drm_i915_private *dev_priv, 
	}



	/*

	 * We don't allow disabling PPGTT for gen9+ as it's a requirement for

	 * We don't allow disabling PPGTT for gen8+ as it's a requirement for

	 * execlists, the sole mechanism available to submit work.

	 */

	if (enable_ppgtt == 0 && INTEL_GEN(dev_priv) < 9)

	if (enable_ppgtt == 0 && !HAS_EXECLISTS(dev_priv))

		return 0;



	if (enable_ppgtt == 1)

drivers/gpu/drm/i915/intel_lrc.c

+3 −2
Original line number Diff line number Diff line
@@ -430,7 +430,7 @@ static u64 execlists_update_context(struct i915_request *rq) 
	 * PML4 is allocated during ppgtt init, so this is not needed

	 * in 48-bit mode.

	 */

	if (ppgtt && !i915_vm_is_48bit(&ppgtt->vm))

	if (!i915_vm_is_48bit(&ppgtt->vm))

		execlists_update_context_pdps(ppgtt, reg_state);



	return ce->lrc_desc;
@@ -1376,6 +1376,7 @@ execlists_context_pin(struct intel_engine_cs *engine, 
	struct intel_context *ce = to_intel_context(ctx, engine);



	lockdep_assert_held(&ctx->i915->drm.struct_mutex);

	GEM_BUG_ON(!(ctx->ppgtt ?: ctx->i915->mm.aliasing_ppgtt));



	if (likely(ce->pin_count++))

		return ce;
@@ -2705,7 +2706,7 @@ static void execlists_init_reg_state(u32 *regs, 
	CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0);

	CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0);



	if (ppgtt && i915_vm_is_48bit(&ppgtt->vm)) {

	if (i915_vm_is_48bit(&ppgtt->vm)) {

		/* 64b PPGTT (48bit canonical)

		 * PDP0_DESCRIPTOR contains the base address to PML4 and

		 * other PDP Descriptors are ignored.