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Commit 49dfccf2 authored by Jigarkumar Zala's avatar Jigarkumar Zala
Browse files

msm: camera: csiphy: Remove unnecessary delay from reset sequence 



Lane enable register reset is not required any delay to reflect the
change. This change removes the unnecesaary delay from lane_enable
register. Also, adding 1us of delay between back to back write in
SW reset register along with condition based refelction of delay.

CRs-Fixed: 2671221
Change-Id: I010570045a97fc1489a84d22ebd39df6f6f14f0a
Signed-off-by: default avatarJigarkumar Zala <jzala@codeaurora.org>
parent 43e3ea9b

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_core.c

+10 −14
Original line number Diff line number Diff line
@@ -71,10 +71,11 @@ void cam_csiphy_reset(struct csiphy_device *csiphy_dev) 
			csiphy_dev->ctrl_reg->csiphy_reset_reg[i].reg_data,

			base +

			csiphy_dev->ctrl_reg->csiphy_reset_reg[i].reg_addr);



		usleep_range(csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay

			* 1000,	csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay

			* 1000 + 10);

		if (csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay > 0)

			usleep_range(

			csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay,

			csiphy_dev->ctrl_reg->csiphy_reset_reg[i].delay

			+ 5);

	}

}
@@ -465,22 +466,16 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev) 
		case CSIPHY_LANE_ENABLE:

			cam_io_w_mb(lane_enable,

				csiphybase + csiphy_common_reg->reg_addr);

			usleep_range(csiphy_common_reg->delay * 1000,

				csiphy_common_reg->delay * 1000 + 10);

			break;

		case CSIPHY_DEFAULT_PARAMS:

			cam_io_w_mb(csiphy_common_reg->reg_data,

				csiphybase + csiphy_common_reg->reg_addr);

			usleep_range(csiphy_common_reg->delay * 1000,

				csiphy_common_reg->delay * 1000 + 10);

			break;

		case CSIPHY_2PH_REGS:

			if (!csiphy_dev->csiphy_info.csiphy_3phase) {

				cam_io_w_mb(csiphy_common_reg->reg_data,

					csiphybase +

					csiphy_common_reg->reg_addr);

				usleep_range(csiphy_common_reg->delay * 1000,

					csiphy_common_reg->delay * 1000 + 10);

			}

			break;

		case CSIPHY_3PH_REGS:
@@ -488,13 +483,14 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev) 
				cam_io_w_mb(csiphy_common_reg->reg_data,

					csiphybase +

					csiphy_common_reg->reg_addr);

				usleep_range(csiphy_common_reg->delay * 1000,

					csiphy_common_reg->delay * 1000 + 10);

			}

			break;

		default:

			break;

		}

		if (csiphy_common_reg->delay > 0)

			usleep_range(csiphy_common_reg->delay,

				csiphy_common_reg->delay + 5);

	}



	while (lane_mask) {
@@ -541,8 +537,8 @@ int32_t cam_csiphy_config_dev(struct csiphy_device *csiphy_dev) 
			break;

			}

			if (reg_array[lane_pos][i].delay > 0) {

				usleep_range(reg_array[lane_pos][i].delay*1000,

					reg_array[lane_pos][i].delay*1000 + 10);

				usleep_range(reg_array[lane_pos][i].delay,

					reg_array[lane_pos][i].delay + 5);

			}

		}

		lane_mask >>= 1;

drivers/cam_sensor_module/cam_csiphy/cam_csiphy_dev.h

+2 −2
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.

 */



#ifndef _CAM_CSIPHY_DEV_H_
@@ -137,7 +137,7 @@ struct csiphy_intf_params { 
 * struct csiphy_reg_t

 * @reg_addr: Register address

 * @reg_data: Register data

 * @delay: Delay

 * @delay: Delay in us

 * @csiphy_param_type: CSIPhy parameter type

 */

struct csiphy_reg_t {

drivers/cam_sensor_module/cam_csiphy/include/cam_csiphy_1_2_3_hwreg.h

+9 −9
Original line number Diff line number Diff line
@@ -26,16 +26,16 @@ struct csiphy_reg_t csiphy_common_reg_1_2_3[] = { 
	{0x081C, 0x5A, 0x00, CSIPHY_2PH_REGS},

	{0x0824, 0x72, 0x00, CSIPHY_2PH_REGS},

	{0x081C, 0x5A, 0x00, CSIPHY_3PH_REGS},

	{0x0800, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x01, 0x02, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x02, 0x00, CSIPHY_2PH_REGS},

	{0x0800, 0x0E, 0x00, CSIPHY_3PH_REGS},

};



struct csiphy_reg_t csiphy_reset_reg_1_2_3[] = {

	{0x0814, 0x00, 0x05, CSIPHY_LANE_ENABLE},

	{0x0814, 0x00, 0x00, CSIPHY_LANE_ENABLE},

	{0x0818, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x081C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x01, 0x02, CSIPHY_DEFAULT_PARAMS},

	{0x0800, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},

};
@@ -247,7 +247,7 @@ csiphy_reg_t csiphy_3ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0990, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0994, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0998, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x098C, 0xAF, 0x01, CSIPHY_DEFAULT_PARAMS},

		{0x098C, 0xAF, 0x64, CSIPHY_DEFAULT_PARAMS},

		{0x0168, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x016C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x015C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -277,7 +277,7 @@ csiphy_reg_t csiphy_3ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0A90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0A8C, 0xAF, 0x01, CSIPHY_DEFAULT_PARAMS},

		{0x0A8C, 0xAF, 0x64, CSIPHY_DEFAULT_PARAMS},

		{0x0368, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x036C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x035C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -307,7 +307,7 @@ csiphy_reg_t csiphy_3ph_v1_2_3_reg[MAX_LANES][MAX_SETTINGS_PER_LANE] = { 
		{0x0B90, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B94, 0x08, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B98, 0x1A, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x0B8C, 0xAF, 0x01, CSIPHY_DEFAULT_PARAMS},

		{0x0B8C, 0xAF, 0x64, CSIPHY_DEFAULT_PARAMS},

		{0x0568, 0x80, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x056C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},

		{0x055C, 0x46, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -348,7 +348,7 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = { 
				{0x544, 0x22, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB4, 0x03, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x03, 0x01, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x03, 0x0A, CSIPHY_DEFAULT_PARAMS},



			}

		},
@@ -368,7 +368,7 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = { 
				{0xB80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB4, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x02, 0x01, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x02, 0x0A, CSIPHY_DEFAULT_PARAMS},

			},

		},

		{
@@ -387,7 +387,7 @@ struct data_rate_settings_t data_rate_delta_table_1_2_3 = { 
				{0xB80, 0x60, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0x9B4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xAB4, 0x01, 0x00, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x01, 0x01, CSIPHY_DEFAULT_PARAMS},

				{0xBB4, 0x01, 0x0A, CSIPHY_DEFAULT_PARAMS},

			},

		}

	}