Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 49c1ae5f authored by Samuel Holland's avatar Samuel Holland Committed by Greg Kroah-Hartman
Browse files

pinctrl: sunxi: Add I/O bias setting for H6 R-PIO 



commit fc153c8f283bf5925615195fc9d4056414d7b168 upstream.

H6 requires I/O bias configuration on both of its PIO devices.
Previously it was only done for the main PIO.

The setting for Port L is at bit 0, so the bank calculation needs to
account for the pin base. Otherwise the wrong bit is used.

Fixes: cc62383f ("pinctrl: sunxi: Support I/O bias voltage setting on H6")
Reviewed-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Tested-by: default avatarHeiko Stuebner <heiko@sntech.de>
Signed-off-by: default avatarSamuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220713025233.27248-3-samuel@sholland.org


Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent b0de3436

drivers/pinctrl/sunxi/pinctrl-sun50i-h6-r.c

+1 −0
Original line number Diff line number Diff line
@@ -105,6 +105,7 @@ static const struct sunxi_pinctrl_desc sun50i_h6_r_pinctrl_data = { 
	.npins = ARRAY_SIZE(sun50i_h6_r_pins),

	.pin_base = PL_BASE,

	.irq_banks = 2,

	.io_bias_cfg_variant = BIAS_VOLTAGE_PIO_POW_MODE_SEL,

};



static int sun50i_h6_r_pinctrl_probe(struct platform_device *pdev)

drivers/pinctrl/sunxi/pinctrl-sunxi.c

+4 −3
Original line number Diff line number Diff line
@@ -616,7 +616,7 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, 
					 unsigned pin,

					 struct regulator *supply)

{

	unsigned short bank = pin / PINS_PER_BANK;

	unsigned short bank;

	unsigned long flags;

	u32 val, reg;

	int uV;
@@ -632,6 +632,9 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, 
	if (uV == 0)

		return 0;



	pin -= pctl->desc->pin_base;

	bank = pin / PINS_PER_BANK;



	switch (pctl->desc->io_bias_cfg_variant) {

	case BIAS_VOLTAGE_GRP_CONFIG:

		/*
@@ -649,8 +652,6 @@ static int sunxi_pinctrl_set_io_bias_cfg(struct sunxi_pinctrl *pctl, 
		else

			val = 0xD; /* 3.3V */



		pin -= pctl->desc->pin_base;



		reg = readl(pctl->membase + sunxi_grp_config_reg(pin));

		reg &= ~IO_BIAS_MASK;

		writel(reg | val, pctl->membase + sunxi_grp_config_reg(pin));