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Commit 494f22dd authored by Sascha Hauer's avatar Sascha Hauer
Browse files

MXC gpio interrupt support: move register definitions to .c file 



Signed-off-by: default avatarSascha Hauer <s.hauer@pengutronix.de>
parent 8afaada2

arch/arm/plat-mxc/gpio.c

+17 −0
Original line number Diff line number Diff line
@@ -29,6 +29,23 @@ 
static struct mxc_gpio_port *mxc_gpio_ports;

static int gpio_table_size;



#define cpu_is_mx1_mx2()	(cpu_is_mx1() || cpu_is_mx2())



#define GPIO_DR		(cpu_is_mx1_mx2() ? 0x1c : 0x00)

#define GPIO_GDIR	(cpu_is_mx1_mx2() ? 0x00 : 0x04)

#define GPIO_PSR	(cpu_is_mx1_mx2() ? 0x24 : 0x08)

#define GPIO_ICR1	(cpu_is_mx1_mx2() ? 0x28 : 0x0C)

#define GPIO_ICR2	(cpu_is_mx1_mx2() ? 0x2C : 0x10)

#define GPIO_IMR	(cpu_is_mx1_mx2() ? 0x30 : 0x14)

#define GPIO_ISR	(cpu_is_mx1_mx2() ? 0x34 : 0x18)

#define GPIO_ISR	(cpu_is_mx1_mx2() ? 0x34 : 0x18)



#define GPIO_INT_LOW_LEV	(cpu_is_mx1_mx2() ? 0x3 : 0x0)

#define GPIO_INT_HIGH_LEV	(cpu_is_mx1_mx2() ? 0x2 : 0x1)

#define GPIO_INT_RISE_EDGE	(cpu_is_mx1_mx2() ? 0x0 : 0x2)

#define GPIO_INT_FALL_EDGE	(cpu_is_mx1_mx2() ? 0x1 : 0x3)

#define GPIO_INT_NONE		0x4



/* Note: This driver assumes 32 GPIOs are handled in one register */



static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)

arch/arm/plat-mxc/include/mach/mx1.h

+0 −14
Original line number Diff line number Diff line
@@ -134,20 +134,6 @@ 
#define GPIO_INT_PORTD		62

#define WDT_INT			63



/* gpio and gpio based interrupt handling */

#define GPIO_DR		 	0x1C

#define GPIO_GDIR	 	0x00

#define GPIO_PSR	 	0x24

#define GPIO_ICR1	 	0x28

#define GPIO_ICR2	 	0x2C

#define GPIO_IMR	 	0x30

#define GPIO_ISR	 	0x34

#define GPIO_INT_LOW_LEV	0x3

#define GPIO_INT_HIGH_LEV	0x2

#define GPIO_INT_RISE_EDGE 	0x0

#define GPIO_INT_FALL_EDGE	0x1

#define GPIO_INT_NONE		0x4



/* DMA */

#define DMA_REQ_UART3_T		2

#define DMA_REQ_UART3_R		3

arch/arm/plat-mxc/include/mach/mx2x.h

+0 −14
Original line number Diff line number Diff line
@@ -150,20 +150,6 @@ 
#define MXC_INT_GPIO		8

#define MXC_INT_CSPI3		6



/* gpio and gpio based interrupt handling */

#define GPIO_DR		 	0x1C

#define GPIO_GDIR	 	0x00

#define GPIO_PSR	 	0x24

#define GPIO_ICR1	 	0x28

#define GPIO_ICR2	 	0x2C

#define GPIO_IMR	 	0x30

#define GPIO_ISR	 	0x34

#define GPIO_INT_LOW_LEV	0x3

#define GPIO_INT_HIGH_LEV	0x2

#define GPIO_INT_RISE_EDGE 	0x0

#define GPIO_INT_FALL_EDGE	0x1

#define GPIO_INT_NONE		0x4



/* fixed DMA request numbers */

#define DMA_REQ_CSI_RX          31

#define DMA_REQ_CSI_STAT        30

arch/arm/plat-mxc/include/mach/mx3x.h

+0 −14
Original line number Diff line number Diff line
@@ -259,20 +259,6 @@ 
#define SYSTEM_REV_MIN		CHIP_REV_1_0

#define SYSTEM_REV_NUM		3



/* gpio and gpio based interrupt handling */

#define GPIO_DR		 	0x00

#define GPIO_GDIR	 	0x04

#define GPIO_PSR	 	0x08

#define GPIO_ICR1	 	0x0C

#define GPIO_ICR2	 	0x10

#define GPIO_IMR	 	0x14

#define GPIO_ISR	 	0x18

#define GPIO_INT_LOW_LEV	0x0

#define GPIO_INT_HIGH_LEV	0x1

#define GPIO_INT_RISE_EDGE	0x2

#define GPIO_INT_FALL_EDGE	0x3

#define GPIO_INT_NONE		0x4



/* Mandatory defines used globally */



#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)