Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 48edde39 authored by welu's avatar welu Committed by Alex Deucher
Browse files

drm/amdgpu: change pp_dpm clk/mclk/pcie input format. 



1. support more than 8 values when setting get_pp_dpm_mclk/
sclk/pcie, the former design just parse command format like
"echo xxxx >　pp_dpm_sclk" and current can parse "echo xx xxx
 xxxx > pp_dpm_sclk" whose operation is more user-friendly
and convinent and can offer more values;
2. be compatible with former design like "xx".
3. add DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_pcie
Bug:KFD-385

Signed-off-by: default avatarwelu <wei.lu2@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 38610f15

drivers/gpu/drm/amd/amdgpu/amdgpu_pm.c

+59 −44
Original line number Diff line number Diff line
@@ -574,10 +574,10 @@ static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev, 
 * the power state and the clock information for those levels.

 *

 * To manually adjust these states, first select manual using

 * power_dpm_force_performance_level.  Writing a string of the level

 * numbers to the file will select which levels you want to enable.

 * E.g., writing 456 to the file will enable levels 4, 5, and 6.

 *

 * power_dpm_force_performance_level.

 * Secondly,Enter a new value for each level by inputing a string that

 * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"

 * E.g., echo 4 5 6 to > pp_dpm_sclk will enable sclk levels 4, 5, and 6.

 */



static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
@@ -602,14 +602,17 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 
	struct amdgpu_device *adev = ddev->dev_private;

	int ret;

	long level;

	uint32_t i, mask = 0;

	char sub_str[2];



	for (i = 0; i < strlen(buf); i++) {

		if (*(buf + i) == '\n')

			continue;

		sub_str[0] = *(buf + i);

		sub_str[1] = '\0';

	uint32_t mask = 0;

	char *sub_str = NULL;

	char *tmp;

	char buf_cpy[count];

	const char delimiter[3] = {' ', '\n', '\0'};



	memcpy(buf_cpy, buf, count+1);

	tmp = buf_cpy;

	while (tmp[0]) {

		sub_str =  strsep(&tmp, delimiter);

		if (strlen(sub_str)) {

			ret = kstrtol(sub_str, 0, &level);



			if (ret) {
@@ -617,8 +620,9 @@ static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev, 
				goto fail;

			}

			mask |= 1 << level;

		} else

			break;

	}



	if (adev->powerplay.pp_funcs->force_clock_level)

		amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
@@ -648,14 +652,17 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 
	struct amdgpu_device *adev = ddev->dev_private;

	int ret;

	long level;

	uint32_t i, mask = 0;

	char sub_str[2];



	for (i = 0; i < strlen(buf); i++) {

		if (*(buf + i) == '\n')

			continue;

		sub_str[0] = *(buf + i);

		sub_str[1] = '\0';

	uint32_t mask = 0;

	char *sub_str = NULL;

	char *tmp;

	char buf_cpy[count];

	const char delimiter[3] = {' ', '\n', '\0'};



	memcpy(buf_cpy, buf, count+1);

	tmp = buf_cpy;

	while (tmp[0]) {

		sub_str =  strsep(&tmp, delimiter);

		if (strlen(sub_str)) {

			ret = kstrtol(sub_str, 0, &level);



			if (ret) {
@@ -663,6 +670,8 @@ static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev, 
				goto fail;

			}

			mask |= 1 << level;

		} else

			break;

	}

	if (adev->powerplay.pp_funcs->force_clock_level)

		amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
@@ -693,14 +702,18 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 
	struct amdgpu_device *adev = ddev->dev_private;

	int ret;

	long level;

	uint32_t i, mask = 0;

	char sub_str[2];



	for (i = 0; i < strlen(buf); i++) {

		if (*(buf + i) == '\n')

			continue;

		sub_str[0] = *(buf + i);

		sub_str[1] = '\0';

	uint32_t mask = 0;

	char *sub_str = NULL;

	char *tmp;

	char buf_cpy[count];

	const char delimiter[3] = {' ', '\n', '\0'};



	memcpy(buf_cpy, buf, count+1);

	tmp = buf_cpy;



	while (tmp[0]) {

		sub_str =  strsep(&tmp, delimiter);

		if (strlen(sub_str)) {

			ret = kstrtol(sub_str, 0, &level);



			if (ret) {
@@ -708,6 +721,8 @@ static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev, 
				goto fail;

			}

			mask |= 1 << level;

		} else

			break;

	}

	if (adev->powerplay.pp_funcs->force_clock_level)

		amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);