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Commit 48ce8f80 authored by Julien Thierry's avatar Julien Thierry Committed by Catalin Marinas
Browse files

arm64: irqflags: Introduce explicit debugging for IRQ priorities 



Using IRQ priority masking to enable/disable interrupts is a bit
sensitive as it requires to deal with both ICC_PMR_EL1 and PSR.I.

Introduce some validity checks to both highlight the states in which
functions dealing with IRQ enabling/disabling can (not) be called, and
bark a warning when called in an unexpected state.

Since these checks are done on hotpaths, introduce a build option to
choose whether to do the checking.

Cc: Will Deacon <will.deacon@arm.com>
Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarJulien Thierry <julien.thierry@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent bd82d4bd

arch/arm64/Kconfig

+11 −0
Original line number Diff line number Diff line
@@ -1436,6 +1436,17 @@ config ARM64_PSEUDO_NMI 


	  If unsure, say N



if ARM64_PSEUDO_NMI

config ARM64_DEBUG_PRIORITY_MASKING

	bool "Debug interrupt priority masking"

	help

	  This adds runtime checks to functions enabling/disabling

	  interrupts when using priority masking. The additional checks verify

	  the validity of ICC_PMR_EL1 when calling concerned functions.



	  If unsure, say N

endif



config RELOCATABLE

	bool

	help

arch/arm64/include/asm/cpufeature.h

+6 −0
Original line number Diff line number Diff line
@@ -617,6 +617,12 @@ static inline bool system_uses_irq_prio_masking(void) 
	       cpus_have_const_cap(ARM64_HAS_IRQ_PRIO_MASKING);

}



static inline bool system_has_prio_mask_debugging(void)

{

	return IS_ENABLED(CONFIG_ARM64_DEBUG_PRIORITY_MASKING) &&

	       system_uses_irq_prio_masking();

}



#define ARM64_SSBD_UNKNOWN		-1

#define ARM64_SSBD_FORCE_DISABLE	0

#define ARM64_SSBD_KERNEL		1

arch/arm64/include/asm/daifflags.h

+7 −0
Original line number Diff line number Diff line
@@ -28,6 +28,10 @@ 
/* mask/save/unmask/restore all exceptions, including interrupts. */

static inline void local_daif_mask(void)

{

	WARN_ON(system_has_prio_mask_debugging() &&

		(read_sysreg_s(SYS_ICC_PMR_EL1) == (GIC_PRIO_IRQOFF |

						    GIC_PRIO_PSR_I_SET)));



	asm volatile(

		"msr	daifset, #0xf		// local_daif_mask\n"

		:
@@ -62,6 +66,9 @@ static inline void local_daif_restore(unsigned long flags) 
{

	bool irq_disabled = flags & PSR_I_BIT;



	WARN_ON(system_has_prio_mask_debugging() &&

		!(read_sysreg(daif) & PSR_I_BIT));



	if (!irq_disabled) {

		trace_hardirqs_on();

arch/arm64/include/asm/irqflags.h

+12 −0
Original line number Diff line number Diff line
@@ -40,6 +40,12 @@ 
 */

static inline void arch_local_irq_enable(void)

{

	if (system_has_prio_mask_debugging()) {

		u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1);



		WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);

	}



	asm volatile(ALTERNATIVE(

		"msr	daifclr, #2		// arch_local_irq_enable\n"

		"nop",
@@ -53,6 +59,12 @@ static inline void arch_local_irq_enable(void) 


static inline void arch_local_irq_disable(void)

{

	if (system_has_prio_mask_debugging()) {

		u32 pmr = read_sysreg_s(SYS_ICC_PMR_EL1);



		WARN_ON_ONCE(pmr != GIC_PRIO_IRQON && pmr != GIC_PRIO_IRQOFF);

	}



	asm volatile(ALTERNATIVE(

		"msr	daifset, #2		// arch_local_irq_disable",

		__msr_s(SYS_ICC_PMR_EL1, "%0"),