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Commit 48321c3d authored by Harry Wentland's avatar Harry Wentland Committed by Alex Deucher
Browse files

drm/amd/display: Read soc_bounding_box from gpu_info (v2) 



[WHY]
We don't want to expose sensitive ASIC information before ASIC release.

[HOW]
Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it
at driver load.

v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex)

Signed-off-by: default avatarHarry Wentland <harry.wentland@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent edee92c3

drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

+9 −1
Original line number Original line Diff line number Diff line
@@ -1432,7 +1432,7 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) 
		adev->gfx.cu_info.max_scratch_slots_per_cu =

		adev->gfx.cu_info.max_scratch_slots_per_cu =

			le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);

			le32_to_cpu(gpu_info_fw->gc_max_scratch_slots_per_cu);

		adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);

		adev->gfx.cu_info.lds_size = le32_to_cpu(gpu_info_fw->gc_lds_size);

		if (hdr->version_minor == 1) {

		if (hdr->version_minor >= 1) {

			const struct gpu_info_firmware_v1_1 *gpu_info_fw =

			const struct gpu_info_firmware_v1_1 *gpu_info_fw =

				(const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +

				(const struct gpu_info_firmware_v1_1 *)(adev->firmware.gpu_info_fw->data +

									le32_to_cpu(hdr->header.ucode_array_offset_bytes));

									le32_to_cpu(hdr->header.ucode_array_offset_bytes));
@@ -1441,6 +1441,14 @@ static int amdgpu_device_parse_gpu_info_fw(struct amdgpu_device *adev) 
			adev->gfx.config.num_packer_per_sc =

			adev->gfx.config.num_packer_per_sc =

				le32_to_cpu(gpu_info_fw->num_packer_per_sc);

				le32_to_cpu(gpu_info_fw->num_packer_per_sc);

		}

		}

#ifdef CONFIG_DRM_AMD_DC_DCN2_0

		if (hdr->version_minor == 2) {

			const struct gpu_info_firmware_v1_2 *gpu_info_fw =

				(const struct gpu_info_firmware_v1_2 *)(adev->firmware.gpu_info_fw->data +

									le32_to_cpu(hdr->header.ucode_array_offset_bytes));

			adev->dm.soc_bounding_box = &gpu_info_fw->soc_bounding_box;

		}

#endif

		break;

		break;

	}

	}

	default:

	default:

drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h

+63 −0
Original line number Original line Diff line number Diff line
@@ -210,6 +210,69 @@ struct gpu_info_firmware_v1_1 { 
	uint32_t num_packer_per_sc;

	uint32_t num_packer_per_sc;

};

};





struct gpu_info_voltage_scaling_v1_0 {

	int state;

	uint32_t dscclk_mhz;

	uint32_t dcfclk_mhz;

	uint32_t socclk_mhz;

	uint32_t dram_speed_mts;

	uint32_t fabricclk_mhz;

	uint32_t dispclk_mhz;

	uint32_t phyclk_mhz;

	uint32_t dppclk_mhz;

};



struct gpu_info_soc_bounding_box_v1_0 {

	uint32_t sr_exit_time_us;

	uint32_t sr_enter_plus_exit_time_us;

	uint32_t urgent_latency_us;

	uint32_t urgent_latency_pixel_data_only_us;

	uint32_t urgent_latency_pixel_mixed_with_vm_data_us;

	uint32_t urgent_latency_vm_data_only_us;

	uint32_t writeback_latency_us;

	uint32_t ideal_dram_bw_after_urgent_percent;

	uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_only; // PercentOfIdealDRAMFabricAndSDPPortBWReceivedAfterUrgLatencyPixelDataOnly

	uint32_t pct_ideal_dram_sdp_bw_after_urgent_pixel_and_vm;

	uint32_t pct_ideal_dram_sdp_bw_after_urgent_vm_only;

	uint32_t max_avg_sdp_bw_use_normal_percent;

	uint32_t max_avg_dram_bw_use_normal_percent;

	unsigned int max_request_size_bytes;

	uint32_t downspread_percent;

	uint32_t dram_page_open_time_ns;

	uint32_t dram_rw_turnaround_time_ns;

	uint32_t dram_return_buffer_per_channel_bytes;

	uint32_t dram_channel_width_bytes;

	uint32_t fabric_datapath_to_dcn_data_return_bytes;

	uint32_t dcn_downspread_percent;

	uint32_t dispclk_dppclk_vco_speed_mhz;

	uint32_t dfs_vco_period_ps;

	unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;

	unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;

	unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;

	unsigned int round_trip_ping_latency_dcfclk_cycles;

	unsigned int urgent_out_of_order_return_per_channel_bytes;

	unsigned int channel_interleave_bytes;

	unsigned int num_banks;

	unsigned int num_chans;

	unsigned int vmm_page_size_bytes;

	uint32_t dram_clock_change_latency_us;

	uint32_t writeback_dram_clock_change_latency_us;

	unsigned int return_bus_width_bytes;

	unsigned int voltage_override;

	uint32_t xfc_bus_transport_time_us;

	uint32_t xfc_xbuf_latency_tolerance_us;

	int use_urgent_burst_bw;

	unsigned int num_states;

	struct gpu_info_voltage_scaling_v1_0 clock_limits[8];

};



/* gpu info payload

 * version_major=1, version_minor=1 */

struct gpu_info_firmware_v1_2 {

	struct gpu_info_firmware_v1_1 v1_1;

	struct gpu_info_soc_bounding_box_v1_0 soc_bounding_box;

};



/* version_major=1, version_minor=0 */

/* version_major=1, version_minor=0 */

struct gpu_info_firmware_header_v1_0 {

struct gpu_info_firmware_header_v1_0 {

	struct common_firmware_header header;

	struct common_firmware_header header;

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+3 −0
Original line number Original line Diff line number Diff line
@@ -557,6 +557,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) 
		init_data.flags.fbc_support = true;

		init_data.flags.fbc_support = true;





	init_data.flags.power_down_display_on_boot = true;

	init_data.flags.power_down_display_on_boot = true;

#ifdef CONFIG_DRM_AMD_DC_DCN2_0

	init_data.soc_bounding_box = adev->dm.soc_bounding_box;

#endif





	/* Display Core create. */

	/* Display Core create. */

	adev->dm.dc = dc_create(&init_data);

	adev->dm.dc = dc_create(&init_data);

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

+7 −0
Original line number Original line Diff line number Diff line
@@ -206,6 +206,13 @@ struct amdgpu_display_manager { 




	const struct firmware *fw_dmcu;

	const struct firmware *fw_dmcu;

	uint32_t dmcu_fw_version;

	uint32_t dmcu_fw_version;

#ifdef CONFIG_DRM_AMD_DC_DCN2_0

	/**

	 * gpu_info FW provided soc bounding box struct or 0 if not

	 * available in FW

	 */

	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;

#endif

};

};





struct amdgpu_dm_connector {

struct amdgpu_dm_connector {

drivers/gpu/drm/amd/display/dc/dc.h

+9 −0
Original line number Original line Diff line number Diff line
@@ -373,6 +373,7 @@ struct dc_bounding_box_overrides { 
struct dc_state;

struct dc_state;

struct resource_pool;

struct resource_pool;

struct dce_hwseq;

struct dce_hwseq;

struct gpu_info_soc_bounding_box_v1_0;

struct dc {

struct dc {

	struct dc_versions versions;

	struct dc_versions versions;

	struct dc_caps caps;

	struct dc_caps caps;
@@ -451,6 +452,14 @@ struct dc_init_data { 




	struct dc_config flags;

	struct dc_config flags;

	uint32_t log_mask;

	uint32_t log_mask;



#ifdef CONFIG_DRM_AMD_DC_DCN2_0

	/**

	 * gpu_info FW provided soc bounding box struct or 0 if not

	 * available in FW

	 */

	const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;

#endif

};

};





struct dc_callback_init {

struct dc_callback_init {